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RTL8139C RTL8139C-lf RTL8139Cl RTL8139Cl-lf 3.3v single-chip fast ethernet controller with power management datasheet rev. 1.6 29 december 2005 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management ii track id: jatr-1076-21 rev. 1. 6 copyright ?2005 realtek semiconductor corp. all rights reserved. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the hardware and software engineer?s general information on the realtek RTL8139C(l) chip. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. revision history revision release date summary 1.5 2005/11/28 format and layout changes. add package id information (section 4.1 package and version identification, page 4). add ordering information (section 14 ordering information, page 63). 1.6 2005/12/29 add sentence ?writing a 1 to any b it will reset that bit, but writing a 0 has no effect? to section 6.6 interrupt status register (offset 003eh-003fh, r/w), page 14. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management iii track id: jatr-1076-21 rev. 1. 6 table of contents 1. general des cription ............................................................................................................ .................................................1 2. features....................................................................................................................... ..........................................................2 3. block diagram .................................................................................................................. ....................................................3 4. pin assignments................................................................................................................ ....................................................4 4.1. package and version identification............................................................................................. ...................................4 5. pin descri ptions............................................................................................................... .....................................................5 5.1. power management/isolation interface........................................................................................... ...............................5 5.2. pci interface .................................................................................................................. ................................................5 5.3. flash/eeprom interface......................................................................................................... ..................................7 5.4. power pins..................................................................................................................... .................................................8 5.5. led interface.................................................................................................................. ...............................................8 5.6. attachment un it inte rface ...................................................................................................... ........................................8 5.7. test and other pins ............................................................................................................ ............................................8 6. register des criptions .......................................................................................................... .................................................9 6.1. receive status register in rx packet header .................................................................................... ..........................11 6.2. transmit status register (t sd0-3)(offset 0010h-001fh, r/w) ..................................................................... ............12 6.3. ersr: early rx status re gister (offset 0036h, r) ............................................................................... ......................13 6.4. command register (offset 0037h, r/w)........................................................................................... ..........................13 6.5. interrupt mask register (offset 003ch-003dh, r/w).............................................................................. ...................14 6.6. interrupt status register (offset 003eh-003fh, r/w)............................................................................ .....................14 6.7. transmit configuration regi ster (offset 0040h-0043h, r/w) ...................................................................... ..............15 6.8. receive configuration regi ster (offset 0044h-0047h, r/w)....................................................................... ...............16 6.9. 9346cr: 93c46 (93c56) command re gister (offset 0050h, r/w)..................................................................... .......19 6.10. config 0: configuration re gister 0 (offset 0051h, r/w) ......................................................................... ...........19 6.11. config 1: configuration re gister 1 (offset 0052h, r/w) ......................................................................... ...........20 6.12. media status register (offset 0058h, r/w)...................................................................................... .......................21 6.13. config 3: configuration re gister3 (offset 0059h, r/w) .......................................................................... ...........21 6.14. config 4: configuration re gister4 (offset 005ah, r/w) .......................................................................... ..........23 6.15. multiple interrupt select regi ster (offset 005ch-005dh, r/w) ................................................................... ..........24 6.16. pci revision id (offset 005eh, r).............................................................................................. ............................24 6.17. transmit status of all descriptors (t sad) register (offset 0060h-0061h, r/w) .................................................24 6.18. basic mode control regist er (offset 0062h-0063h, r/w).......................................................................... ............25 6.19. basic mode status regi ster (offset 0064h-0065h, r) ............................................................................. ................25 6.20. auto-negotiation advertisement register (offset 0066h-0067h, r/w).............................................................. ....26 6.21. auto-negotiation link partner ability register (offset 0068h-0069h, r)......................................................... .....27 6.22. auto-negotiation expansion regi ster (offset 006ah-006bh, r).................................................................... ........27 6.23. disconnect counter (o ffset 006ch-006dh, r) ..................................................................................... ...................27 6.24. false carrier sense counter (offset 006eh-006fh, r)............................................................................ ................28 6.25. nway test register (offset 0070h-0071h, r/w)................................................................................... .................28 6.26. rx_er counter (offset 0072h-0073h, r).......................................................................................... .....................28 6.27. cs configuration regist er (offset 0074h-0075h, r/w)............................................................................ ..............28 6.28. flash memory read/write regi ster (offset 00d4h-00d7h, r/w)..................................................................... .....29 6.29. config5: configura tion register 5 (o ffset 00d8h, r/w) .......................................................................... ..............29 6.30. function event register (offset 00f0h-00f3h, r/w) .............................................................................. ...............30 6.31. function event mask register (offset 00f4h-00f7h, r/w) ......................................................................... ..........31 6.32. function present state regist er (offset 00f8h-00fbh, r) ........................................................................ ..............31 6.33. function force event register (offset 00fch-00ffh, w) .......................................................................... ............32 7. eeprom contents (93c46 or 93c56)............................................................................................... ..............................33 7.1. summary of eepro m registers .................................................................................................... .............................35 7.2. summary of eeprom power management registers ................................................................................... .............35 8. pci configuration space registers .............................................................................................. ....................................36 8.1. pci configurati on space table.................................................................................................. ..................................36 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management iv track id: jatr-1076-21 rev. 1. 6 8.2. pci configurati on space functions .............................................................................................. ...............................38 8.3. default values after po wer-on (rstb asserted) .................................................................................. ......................42 8.3.1. pci configurati on space table.................................................................................................. ..........................42 8.4. pci power manage ment functions ................................................................................................. .............................44 8.5. vital product da ta (vpd) ....................................................................................................... .....................................46 9. functional de scription......................................................................................................... ..............................................47 9.1. transmit op eration............................................................................................................. ..........................................47 9.2. receive op eration .............................................................................................................. ..........................................47 9.3. line quality monitor........................................................................................................... .........................................47 9.4. clock recovery module.......................................................................................................... .....................................47 9.5. loopback operation............................................................................................................. ........................................47 9.6. tx encapsulation............................................................................................................... ...........................................47 9.7. collision ...................................................................................................................... .................................................47 9.8. rx decapsulation ............................................................................................................... ..........................................48 9.9. flow control ................................................................................................................... .............................................48 9.9.1. control frame transmission ..................................................................................................... ...........................48 9.9.2. control fram e recep tion ........................................................................................................ .............................48 9.10. led functions .................................................................................................................. .......................................49 9.10.1. 10/100mbps link monitor ........................................................................................................ ...........................49 9.10.2. led_rx......................................................................................................................... ......................................49 9.10.3. led_tx......................................................................................................................... ......................................49 9.10.4. led_tx+led_rx .................................................................................................................. ...........................50 10. application diagram............................................................................................................ ..............................................51 11. electrical char acteristics..................................................................................................... ..............................................52 11.1. temperature li mit ra tings...................................................................................................... .................................52 11.2. dc charact eristics............................................................................................................. .......................................52 11.2.1. supply voltage ................................................................................................................. ....................................52 11.3. ac charact eristics............................................................................................................. .......................................53 11.3.1. flash/boot rom timing.......................................................................................................... .....................53 11.3.2. pci bus operation timing....................................................................................................... ............................55 12. mechanical dimensi ons (128-pin qfp)............................................................................................ ................................61 13. mechanical dimensi ons (128-pin lqfp) ........................................................................................... ..............................62 14. ordering information ........................................................................................................... .............................................63 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 1 track id: jatr-1076-21 rev. 1. 6 1. general description the realtek RTL8139C(l) is a highly integrated and co st-effective single-chip fast ethernet controller that provides 32-bit performance, pci bus master capability, and full compliance with ieee 802.3u 100base-t specifications and ieee 802.3x full duplex flow control. it also supports advanced configuration power management interface (acpi), pci power management for modern operating systems that are capable of operating system directed power management (ospm) to achieve the most efficient power management possible. the RTL8139Cl is suitable for applications such as cardbus or mobile devices with a built-in network controller. the cis data can be stored in either a 93c56 eeprom or expansion rom. in addition to the acpi feature, the RTL8139C(l) also supports remote wake-up (including amd magic packet, linkchg, and microsoft wake-up frame) in both acpi and apm environments. the RTL8139C(l) is capable of performing an internal reset through the application of auxiliary power. when auxiliary power is on and the main power remains off, the RTL8139C(l ) is ready and waiting for the magic packet or link change to wake the system up. also, the lwake pi n provides 4 different output signals including active high, active low, positive pulse, and negative pulse. the versatility of the RTL8139C(l) lwake pin provides motherboards with the wake-on-lan (wol ) function. the RTL8139C(l) also supports analog auto-power-down, that is, the anal og part of the RTL8139C(l) can be shut down temporarily according to user requirements or when the RTL8139C(l) is in a power down state with the wakeup function disabled. in addition, when the analog part is shut down and the is olateb pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning a nd power consumption of the RTL8139C(l) will be negligible. the RTL8139C(l) also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own pci power ma nagement registers in pci configuration space. the pci vital product data (vpd) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8139C(l) lan card). the information may consist of part number, serial number, and other detailed information. to provide cost down support, the r tl8139c(l) is capable of using a 25mhz crystal or osc as its internal clock source. the RTL8139C(l) keeps network maintenance costs low and eliminates usage barriers. it is the easiest way to upgrade a network from 10 to 100mbps. it also supports full-duplex operation, making 200mbps bandwidth possible at no additional cost. to improve compatibility with other brands? products, the RTL8139C(l) is also capable of receiving packets with interframegap no less than 40 bit-time. the RTL8139C(l) is highly integrated and requires no ?glue? logic or external memory. it includes an interface for a boot rom and can be used in diskless worksta tions, providing maximum network security and ease of management. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 2 track id: jatr-1076-21 rev. 1. 6 2. features z 128 pin qfp/lqfp z integrated fast ethernet mac, physical chip, and transceiver in one chip z 10 mb/s and 100 mb/s operation z supports 10 mb/s and 100 mb/s n-way auto-negotiation operation z pci local bus single-chip fast ethernet controller ? compliant to pci revision 2.2 ? supports pci clock 16.75mhz-40mhz ? supports pci target fast back-to-back transaction ? provides pci bus master data transfers and pci memory space or i/o space mapped data transfers of RTL8139C(l)'s operational registers ? supports pci vpd (vital product data) ? supports acpi, pci power management z supports cardbus. the cis can be stored in 93c56 or expansion rom z supports up to 128k bytes boot rom interface for both eprom and flash memory z supports 25mhz crystal or 25mhz osc as the internal clock source. the frequency deviation of either crystal or osc must be within 50 ppm. z compliant to pc99 standard z supports wake-on-lan func tion and remote wake-up (magic packet*, linkchg and microsoft ? wake-up frame) z supports 4 wake-on-lan (wol) signals (active high, active low, positive pulse, and negative pulse) z supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off z supports auxiliary power auto-detect, and sets the related capability of power management registers in pci configuration space. z includes a programmable, pci burst size and early tx/rx threshold. z supports a 32-bit general-purpose timer with the external pci clock as clock source, to generate timer-interrupt z contains two large (2kbyte) independent receive and transmit fifo?s z advanced power saving mode when lan function or wakeup function is not used z uses 93c46 (64*16-bit eeprom) or 93c56 (128*16-bit eeprom) to store resource configuration, id parameter, and vpd data. the 93c56 can also be used to store the cis da ta structure for cardbus application. z supports led pins for various network activity indications z supports digital and anal og loopback capability on both ports z half/full duplex capability z supports full duplex flow control (ieee 802.3x) z 3.3v power supply with 5v tolerant i/os. * third-party brands and names are the property of their respective owners. note: the model number of the qfp package is RTL8139C. the lqfp package model number is RTL8139Cl. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 3 track id: jatr-1076-21 rev. 1. 6 3. block diagram mii interface interrupt control logic fifo transmit/ receive logic interface early interrupt control logic fifo control logic packet type discriminator power control logic pci interface + register packet length register early interrupt threshold register boot rom interface eeprom interface led driver rxin+ rxin- txo+ txo - rxc 25m 25m txc 25m txd rxd td+ variable current 3 level driver master ppl adaptive equalizer peak detect 3 level comparator control voltage mlt-3 to nrzi serial to parrallel ck data slave pll parrallel to serial baseline wander correction 5b 4b decoder data alignment descrambler 4b 5b encoder scrambler 10/100 half/full switch logic 10/100m auto-negotiation control logic manchester coded waveform 10m output waveform shaping data recovery receive low pass filter rxd rxc 25m txd txc 25m txd10 txc10 rxd10 rxc10 link pulse mii interface 10m 100m pci interface mac phy transceiver www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 4 track id: jatr-1076-21 rev. 1. 6 4. pin assignments figure 1. pin assignments 4.1. package and version identification lead (pb)-free package is indicated by an ?l? in the location marked ?t? in figure 1. the version number is shown in the location marked ?v?. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 5 track id: jatr-1076-21 rev. 1. 6 5. pin descriptions in order to reduce pin count, and therefore size and cost, some pins have multiple f unctions. in those cases, the functions are separated with a ?/? symbol. refer to the pin assignment diagram for a graphical representation. 5.1. power management/isolation interface symbol type pin no description pmeb (pme#) o/d 76 power management event: open drain, active low. used by the RTL8139C(l) to request a change in its current power management state and/or to indicate that a power management event has occurred. isolateb (isolate#) i 95 isolate pin: active low. used to isolate the RTL8139C(l) from the pci bus. the RTL8139C(l) does not drive its pci outputs (excluding pme#) and does not sample its pci input (including rst# and pciclk) as long as the isolate pin is asserted. lwake/ cstschg o 83 lan wake-up signal (when ca rdb_en=0, bit2 config3): this signal is used to inform the motherboard to execute th e wake-up process. the motherboard must support wake-on-lan (wol). there are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that may be asserted from the lwake pin. please refer to the lwact bit in the config1 register and the lwptn bit in the config4 register for the setting of this output signal. the default output is an active high signal. once a pme event is received, the lwake and pmeb assert at the same time when the lwpme (bit4, config4) is set to 0. if the lwpme is set to 1, the lwake asserts only when the pmeb a sserts and the isolateb is low. cstschg signal (when cardb_en=1, bit2 config3): this signal is used in cardbus applications only and is used to inform the motherboard to execute the wake-up process whenever a pme event o ccurs. this is always an active high signal, and the setting of lwact (bit 4, config1), lwptn (bit2, config4), and lwpme (bit4, config4) mean nothing in this case. this pin is a 3.3v signaling output pin. 5.2. pci interface symbol type pin no description ad31-0 t/s 120-123, 125-128, 4-6, 8-11, 13, 26-29, 31-34, 37-39, 41-45 pci address and data multiplexed pins. c/be3-0 t/s 2, 14, 24, 36 pci bus command and byte enables multiplexed pins. clk i 116 clock: this pci bus clock provides timing for all transactions and bus phases, and is input to pci devices. the rising edge defines the start of each phase. the clock frequenc y ranges from 0 to 33mhz. clkrunb i/o 75 clock run: this signal is used by the RTL8139C(l) to request starting (or speeding up) the clock, clk. clkrunb also indicates the clock status. for the RTL8139C(l), clkrunb is an open drain output as well as an input. the RTL8139C(l) requests the central resource to start, speed up, or maintain the interface clock by the assertion of clkrunb. for the host system, it is an s/t/s signal. the host system (central resource) is responsible for maintaining clkrunb asserted, and for driving it high to the negated (deasserted) state. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 6 track id: jatr-1076-21 rev. 1. 6 symbol type pin no description devselb s/t/s 19 device select: as a bus master, the RTL8139C(l) samples this signal to insure that a pci target recognizes the destination address for the data transfer. as a target, the RTL8139C(l) asserts this signal low when it recognizes its target address after frameb is asserted. frameb s/t/s 15 cycle frame: as a bus master, this pin indicates the beginning and duration of an access. frameb is asse rted low to indicate the start of a bus transaction. while frameb is asserted, data transfer continues. when frameb is deasserted, the transaction is in the final data phase. as a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. gntb i 117 grant: this signal is asserted low to indicate to the RTL8139C(l) that the central arbiter has granted ownership of the bus to the RTL8139C(l). this input is used when the RTL8139C(l) is acting as a bus master. reqb t/s 118 request: the RTL8139C(l) will assert this signal low to request the ownership of the bus from the central arbiter. idsel i 3 initialization device select : this pin allows the RTL8139C(l) to identify when configuration read/write transactions are intended for it. intab o/d 114 interrupt a: used to request an interrupt. it is asserted low when an interrupt condition occurs, as defined by the interrupt status, interrupt mask and interrupt enable registers. irdyb s/t/s 16 initiator ready : this indicates the initiating agent?s ability to complete the current data phase of the transaction. as a bus master, this signal will be asserted low when the RTL8139C(l) is ready to complete the current data phase transaction. this signal is used in conjunction with the trdyb signal. data transaction takes place at the rising edge of clk when both irdyb and trdyb are asserted low. as a targ et, this signal indicates that the master has put data on the bus. trdyb s/t/s 17 target ready: this indicates the target agent?s ability to complete the current phase of the transaction. as a bus master, this signal indicates th at the target is ready for the data during write operations and with the data during read operations. as a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. this signal is used in conjunction with the irdyb signal. da ta transaction takes place at the rising edge of clk when both irdyb and trdyb are asserted low. par t/s 23 parity: this signal indicates even parity across ad31-0 and c/be3-0 including the par pin. as a master, par is asserted during address and write data phases. as a target, par is asserted during read data phases. perrb s/t/s 21 parity error: when the RTL8139C(l) is the bus master and a parity error is detected, the RTL8139C(l) asserts both serr bit in isr and configuration space command bit 8 (serrb enable). next, it completes the current data burst transaction, then stops operation and resets itself. after the host clears the system error, the RTL8139C(l) continues its operation. when the RTL8139C(l) is the bus target and a parity error is detected, the RTL8139C(l) asserts this perrb pin low. serrb o/d 22 system error: if an address parity error is detected and configuration www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 7 track id: jatr-1076-21 rev. 1. 6 symbol type pin no description space status register bit 15 (detect ed parity error) is enabled, RTL8139C(l) asserts both serrb pin low and bit 14 of status register in configuration space. stopb s/t/s 20 stop: indicates the current target is requesting the master to stop the current transaction. rstb i 115 reset: when rstb is asserted low, the RTL8139C(l) performs an internal system hardware reset. rs tb must be held for a minimum of 120 ns. 5.3. flash/eeprom interface symbol type pin no description ma16-3 ma8 o i/o 70-63, 61, 60, 57, 53-51 61 boot prom address bus: these pins are used to access up to a 128k-byte flash memory or eprom. output pin as part of boot prom (or flash) address bus after pci reset. input pin as aux. power detect pin to detect if aux. power exists or not, when initial power-on or pci reset is asserted. besides connecting this pin to boot prom, it should be pulled high to the aux. power via a resistor to detect aux. power. if this pin is not pulled high to aux. power, the RTL8139C(l) assumes that no aux. power exists. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. ma6/9356sel i/o 57 when this pin is pulled high with a 10k ? resistor, the 93c56 eeprom is used to store the resource data and cis for the RTL8139C(l). the RTL8139C(l) latches the status of this pin at power-up to determine what eeprom (93c46 or 93c56) is used, afterwards, this pin is used as ma6. ma2/eesk o 49 the ma2-0 pins are switched to eesk, eedi, eedo in 93c46 (93c56) programming or auto-load mode. ma1/eedi o 48 ma0/eedo o, i 47 eecs o 50 93c46 (93c56) chip select md0-7 i/o 108, 107, 105-100 boot prom data bus romcsb o 110 rom chip select: this is the chip select signal of the boot prom. oeb o 88 output enable: this enables the output buffer of the boot prom or flash memory during a read operation. web o 89 write enable: this signal strobes data into the flash memory during a write cycle. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 8 track id: jatr-1076-21 rev. 1. 6 5.4. power pins symbol type pin no description vdd p 1, 12, 25, 35, 46, 58, 59, 106, 109, 119 digital power +3.3v p 77, 90, 96 analog power +3.3v gnd p 7, 18, 30, 40, 55, 56, 62, 111, 112, 113, 124 digital ground p 74, 80, 85, 93 analog ground 5.5. led interface symbol type pin no description led0, 1, 2 o 99, 98, 97 led pins leds1-0 00 01 10 11 led0 tx/rx tx/rx tx tx led1 link100 link10/100 link10/100 link100 led2 link10 full rx link10 during power down mode, the leds are off. 5.6. attachment unit interface symbol type pin no description txd+ txd- o o 92 91 100/10base-t transmit (tx) data rxin+ rxin- i i 87 86 100/10base-t receive (rx) data x1 i 79 25 mhz crystal/osc. input x2 o 78 crystal feedback output: this output is used in crystal connection only. it must be left open when x1 is driven with an external 25 mhz oscillator. 5.7. test and other pins symbol type pin no description rtt2-3 test 81, 82 chip test pins. rtset i/o 84 this pin must be pulled low by a 1.7k ? resistor. nc - 54, 71, 72, 73, 94 reserved www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 9 track id: jatr-1076-21 rev. 1. 6 6. register descriptions the RTL8139C(l) provides the following se t of operational registers mapped in to pci memory space or i/o space. offset r/w tag description 0000h r/w idr0 id register 0: the id registers 0-5 are only permitted to read/write by 4-byte access. read access can be byte, word, or double word access. the initial value is autolo aded from the eeprom ethernetid field. 0001h r/w idr1 id register 1 0002h r/w idr2 id register 2 0003h r/w idr3 id register 3 0004h r/w idr4 id register 4 0005h r/w idr5 id register 5 0006h-0007h - - reserved 0008h r/w mar0 multicast register 0: the mar registers 0-7 are only permitted to read/write by 4-byte access. read access can be byte, word, or double word access. driver is responsible for initializing these registers. 0009h r/w mar1 multicast register 1 000ah r/w mar2 multicast register 2 000bh r/w mar3 multicast register 3 000ch r/w mar4 multicast register 4 000dh r/w mar5 multicast register 5 000eh r/w mar6 multicast register 6 000fh r/w mar7 multicast register 7 0010h-0013h r/w tsd0 transmit status of descriptor 0 0014h-0017h r/w tsd1 transmit status of descriptor 1 0018h-001bh r/w tsd2 transmit status of descriptor 2 001ch-001fh r/w tsd3 transmit status of descriptor 3 0020h-0023h r/w tsad0 transmit start address of descriptor0 0024h-0027h r/w tsad1 transmit start address of descriptor1 0028h-002bh r/w tsad2 transmit start address of descriptor2 002ch-002fh r/w tsad3 transmit start address of descriptor3 0030h-0033h r/w rbstart receive (rx) buffer start address 0034h-0035h r erbcr early receive (rx) byte count register 0036h r ersr early rx status register 0037h r/w cr command register 0038h-0039h r/w capr current address of packet read (the initial value is 0fff0h) 003ah-003bh r cbr current buffer address: the initial value is 0000h. it reflects total received byte-count in the rx buffer. 003ch-003dh r/w imr interrupt mask register 003eh-003fh r/w isr interrupt status register 0040h-0043h r/w tcr transmit (tx) configuration register 0044h-0047h r/w rcr receive (rx) configuration register 0048h-004bh r/w tctr timer count register: this register contains a 32-bit general-purpose timer. writing any value to this 32-bit register will reset the original timer and begin to count from zero. 004ch-004fh r/w mpc missed packet counter: indicates the number of packets discarded due to rx fifo overflow. it is a 24-bit counter. after s/w reset, mpc is cleared. only the lower 3 bytes are valid. when any value is written, mpc will be reset also. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 10 track id: jatr-1076-21 rev. 1. 6 offset r/w tag description 0050h r/w 9346cr 93c46 (93c56) command register 0051h r/w config0 configuration register 0 0052h r/w config1 configuration register 1 0053h - - reserved 0054h-0057h r /w timerint timer interrupt register: once having written a nonzero value to this register, the timeout bit of isr register will be set whenever the tctr reaches to this value. the ti meout bit will never be set as long as timerint register is zero. 0058h r/w msr media status register 0059h r/w config3 configuration register 3 005ah r/w config4 configuration register 4 005bh - - reserved 005ch-005dh r/w mulint multiple interrupt select 005eh r rerid pci revision id = 10h 005fh - - reserved 0060h-0061h r tsad transmit status of all descriptors 0062h-0063h r/w bmcr basic mode control register 0064h-0065h r bmsr basic mode status register 0066h-0067h r/w anar auto-negotiation advertisement register 0068h-0069h r anlpar auto-negotiation link partner register 006ah-006bh r aner auto-negotiation expansion register 006ch-006dh r dis disconnect counter 006eh-006fh r fcsc false carrier sense counter 0070h-0071h r/w nwaytr n-way test register 0072h-0073h r rec rx_er counter 0074h-0075h r/w cscr cs configuration register 0076-0077h - - reserved 0078h-007bh r/w phy1_parm phy parameter 1 007ch-007fh r/w tw_parm twister parameter 0080h r/w phy2_parm phy parameter 2 0081-0083h - - reserved 0084h r/w crc0 power management crc register0 for wakeup frame0 0085h r/w crc1 power management crc register1 for wakeup frame1 0086h r/w crc2 power management crc register2 for wakeup frame2 0087h r/w crc3 power management crc register3 for wakeup frame3 0088h r/w crc4 power management crc register4 for wakeup frame4 0089h r/w crc5 power management crc register5 for wakeup frame5 008ah r/w crc6 power management crc register6 for wakeup frame6 008bh r/w crc7 power management crc register7 for wakeup frame7 008ch?0093h r/w wakeup0 power management wakeup frame0 (64bit) 0094h?009bh r/w wakeup1 power management wakeup frame1 (64bit) 009ch?00a3h r/w wakeup2 power management wakeup frame2 (64bit) 00a4h?00abh r/w wakeup3 power management wakeup frame3 (64bit) 00ach?00b3h r/w wakeup4 power management wakeup frame4 (64bit) 00b4h?00bbh r/w wakeup5 power management wakeup frame5 (64bit) 00bch?00c3h r/w wakeup6 power management wakeup frame6 (64bit) 00c4h?00cbh r/w wakeup7 power management wakeup frame7 (64bit) 00cch r/w lsbcrc0 lsb of the mask byte of wakeup frame0 within offset 12 to 75 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 11 track id: jatr-1076-21 rev. 1. 6 offset r/w tag description 00cdh r/w lsbcrc1 lsb of the mask byte of wakeup frame1 within offset 12 to 75 00ceh r/w lsbcrc2 lsb of the mask byte of wakeup frame2 within offset 12 to 75 00cfh r/w lsbcrc3 lsb of the mask byte of wakeup frame3 within offset 12 to 75 00d0h r/w lsbcrc4 lsb of the mask byte of wakeup frame4 within offset 12 to 75 00d1h r/w lsbcrc5 lsb of the mask byte of wakeup frame5 within offset 12 to 75 00d2h r/w lsbcrc6 lsb of the mask byte of wakeup frame6 within offset 12 to 75 00d3h r/w lsbcrc7 lsb of the mask byte of wakeup frame7 within offset 12 to 75 00d4h-00d7h r/w flash flash memory read/write register 00d8h r/w config5 configuration register 5 00d9h-00efh - - reserved 00f0h-00f3h r/w fer function event register (cardbus only) 00f4h-00f7h r/w femr function event mask register (cardbus only) 00f8h-00fbh r fpsr function present state register (cardbus only) 00fch-00ffh w ffer function force event register (cardbus only) 6.1. receive status register in rx packet header bit r/w symbol description 15 r mar multicast address received: this bit set to 1 indicates that a multicast packet is received. 14 r pam physical address matched: this bit set to 1 indicates that the destination address of this packet matches the value written in id registers. 13 r bar broadcast address received: this bit set to 1 indicates that a broadcast packet is received. bar, mar bit will not be set simultaneously. 12-6 - - reserved 5 r ise invalid symbol error: (100base-tx only) this bit set to 1 indicates that an invalid symbol was encountered during the reception of this packet. 4 r runt runt packet received: this bit set to 1 indicates that the received packet length is smaller than 64 bytes ( i.e. media header + data + crc < 64 bytes ) 3 r long long packet: this bit set to 1 indicates that the size of the received packet exceeds 4k bytes. 2 r crc crc error: when set, indicates that a crc error occurred on the received packet. 1 r fae frame alignment error: when set, indicates that a frame alignment error occurred on this received packet. 0 r rok receive ok: when set, indicates that a good packet is received. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 12 track id: jatr-1076-21 rev. 1. 6 6.2. transmit status register (tsd0-3)(offset 0010h-001fh, r/w) the read-only bits (crs, tabt, owc, c dh, ncc3-0, tok, tun) will be cleared by the RTL8139C(l) when the transmit byte count (bit12-0) in the corre sponding tx descriptor is written. it is not affected when soft ware writes to these bits. thes e registers are only permitted to write by doubl e-word access. after a software reset, a ll bits except the own bit are reset to ? 0?. bit r/w symbol description 31 r crs carrier sense lost: this bit is set to 1 when the carrier is lost during transmission of a packet. 30 r tabt transmit abort: this bit is set to 1 if the transmission of a packet was aborted. this bit is read only, writing to this bit is not affected. 29 r owc out of window collision: this bit is set to 1 if the RTL8139C(l) encountered an "out of window" co llision during the transmission of a packet. 28 r cdh cd heart beat: the same as rtl8139(a/b). this bit is cleared in the 100 mbps mode. 27-24 r ncc3-0 number of collision count: indicates the number of collisions encountered during the transmission of a packet. 23-22 - - reserved 21-16 r/w ertxth5-0 early tx threshold: specifies the threshold level in the tx fifo to begin the transmission. when the byte count of the data in the tx fifo reaches this level, (or the fifo cont ains at least one complete packet) the RTL8139C(l) will transmit this packet. 000000 = 8 bytes these fields count from 000001 to 111111 in unit of 32 bytes. this threshold must be a voided from exceeding 2k byte. 15 r tok transmit ok: set to 1 indicates that the transmission of a packet was completed successfully and no transmit underrun occurs. 14 r tun transmit fifo underrun: set to 1 if the tx fifo was exhausted during the transmission of a packet. the RTL8139C(l) can re-transfer data if the tx fifo underruns and can also transmit the packet to the wire successfully even though the tx fifo underruns. that is, when tsd=1, tsd=0 and isr=1 (or isr=1). 13 r/w own own: the RTL8139C(l) sets this bit to 1 when the tx dma operation of this descriptor was completed. the driver must set this bit to 0 when the transmit byte count (bit0-12) is written. the default value is 1. 12-0 r/w size descriptor size: the total size in bytes of the data in this descriptor. if the packet length is more than 1792 byte (0700h), the tx queue will be invalid, i.e. the next descriptor will be written only after the own bit of that long packet's descriptor has been set. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 13 track id: jatr-1076-21 rev. 1. 6 6.3. ersr: early rx status register (offset 0036h, r) bit r/w symbol description 7-4 - - reserved 3 r ergood early rx good packet: this bit is set whenever a packet is completely received and the packet is good. this bit is cleared when writing 1 to it, 2 r erbad early rx bad packet: this bit is set whenever a packet is completely received and the packet is bad. writing 1 will clear this bit. 1 r erovw early rx overwrite: this bit is set when the RTL8139C(l)'s local address pointer is equal to capr. in the early mode, this is different from buffer overflow. it happens that the RTL8139C(l) detected an rx error and wanted to fill another packet data from the beginning address of that error packet. writing 1 will clear this bit. 0 r erok early rx ok: the power-on value is 0. it is set when the rx byte count of the arriving packet ex ceeds the rx threshold. after the whole packet is received, the RTL8139C(l) will set rok or rer in isr and clear this bit simultaneously. setting this bit will invoke a rok interrupt. 6.4. command register (offset 0037h, r/w) this register is used for issuing comma nds to the RTL8139C(l). these commands are issued by setting the corresponding bits for the function. a global software reset along with individual reset and enable/dis able for transmitter and receiver are provided here. bit r/w symbol description 7-5 - - reserved 4 r/w rst reset: setting to 1 forces the RTL8139C(l) to a software reset state which disables the transmitter and receiver, reinitializes the fifos, resets the system buffer pointer to the initial value (tx buffer is at tsad0, rx buffer is empty). the values of idr0-5 and mar0-7 and pci configuration space will have no ch anges. this bit is 1 during the reset operation, and is cleared to 0 by the RTL8139C(l) when the reset operation is complete. 3 r/w re receiver enable: when set to 1, and the recei ve state machine is idle, the receive machine beco mes active. this bit w ill read back as a 1 whenever the receive st ate machine is active. after initial power-up, software must insure that the r eceiver has completely reset before setting this bit. 2 r/w te transmitter enable: when set to 1, and the transmit state machine is idle, then the transmit state machine becomes active. this bit will read back as a 1 whenever the transmit state machine is active. after initial power-up, software must insure that the transmitter has completely reset before setting this bit. 1 - - reserved 0 r bufe buffer empty: the rx buffer is empty; ther e is no packet stored in the rx buffer ring. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 14 track id: jatr-1076-21 rev. 1. 6 6.5. interrupt mask register (offset 003ch-003dh, r/w) this register masks the interrupts that can be generated from the isr. writing a ?1? to the bit enables the corresponding inter rupt. during a hardware reset, all mask bits are cleared. setting a ma sk bit allows the corresponding bit in the isr to cause an inte rrupt. isr bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit. bit r/w symbol description 15 r/w serr system error interrupt: 1 => enable, 0 => disable. 14 r/w timeout time out interrupt: 1 => enable, 0 => disable. 13 r/w lenchg cable length change interrupt : 1 => enable, 0 => disable. 12-7 - - reserved 6 r/w fovw rx fifo overflow interrupt: 1 => enable, 0 => disable. 5 r/w pun/linkchg packet underrun/link change interrupt: 1 => enable, 0 => disable. 4 r/w rxovw rx buffer overflow interrupt: 1 => enable, 0 => disable. 3 r/w ter transmit error interrupt: 1 => enable, 0 => disable. 2 r/w tok transmit ok interrupt: 1 => enable, 0 => disable. 1 r/w rer receive error interrupt: 1 => enable, 0 => disable. 0 r/w rok receive ok interrupt: 1 => enable, 0 => disable. 6.6. interrupt status register (offset 003eh-003fh, r/w) this register indicates the source of an interrupt when the inta pin goes active. enabling the corresponding bits in the interr upt mask register (imr) allows bits in this register to produce an interrupt. when an interrupt is active, one of more bits in this register are set to a ?1?. the interrupt status register reflects all current pending interrupts, regardless of the state of th e corresponding mask bit in the imr. writing a 1 to any b it will reset that bit, but writing a 0 has no effect. bit r/w symbol description 15 r/w serr system error: set to 1 when the RTL8139C(l) signals a system error on the pci bus. 14 r/w timeout time out: set to 1 when the tctr regist er reaches to the value of the timerint register. 13 r/w lenchg cable length change: cable length is changed after receiver is enabled. 12 - 7 - - reserved 6 r/w fovw rx fifo overflow: set when an overflow occurs on the rx status fifo. 5 r/w pun/linkchg packet underrun/link change: set to 1 when capr is written but rx buffer is empty, or when link status is changed. 4 r/w rxovw rx buffer overflow: set when receive (rx) buffer ring storage resources have been exhausted. 3 r/w ter transmit (tx) error: indicates that a packet transmission was aborted, due to excessive collisi ons, according to the txrr's setting 2 r/w tok transmit (tx) ok: indicates that a packet transmission is completed successfully. 1 r/w rer receive (rx) error: indicates that a packet has either crc error or frame alignment error (fae). the co llided frame will not be recognized as crc error if the length of this frame is shorter than 16 byte. 0 r/w rok receive (rx) ok: in normal mode, indicates the successful completion of a packet reception. in early mode, indicates that the rx byte count of the arriving packet exceeds the early rx threshold. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 15 track id: jatr-1076-21 rev. 1. 6 6.7. transmit configuration register (offset 0040h-0043h, r/w) this register defines the transmit configuration for the RTL8139C (l). it controls such functions as loopback, heartbeat, auto transmit padding, programmable inter-frame gap, fill a nd drain thresholds, and maximum dma burst size. bit r/w symbol description 31 - - reserved hardware version id: bit30 bit29 bit28 bit27 bit26 bit23 rtl8139 1 1 0 0 0 0 rtl8139a 1 1 1 0 0 0 rtl8139a-g 1 1 1 0 0 1 rtl8139b 1 1 1 1 0 0 rtl8130 1 1 1 1 1 0 RTL8139C 1 1 1 0 1 0 reserved all other combination 30-26 r hwverid 25-24 r/w ifg1, 0 interframe gap time: this field allows adjustment of the interframe gap time below the standards of 9.6 us for 10mbps, 960 ns for 100mbps. the time can be programmed from 9.6 us to 8.4 us (10mbps) and 960ns to 840ns (100mbps). note that any value other than (1, 1) will violate the ieee 802.3 standard. the formula for the inter frame gap is: 10 mbps 8.4us + 0.4(ifg(1:0)) us 100 mbps 840ns + 40(ifg(1:0)) ns 23 r 8139a-g rtl8139a rev.g id = 1. for others, this bit is 0. 22-19 - - reserved 18, 17 r/w lbk1, lbk0 loopback test: there will be no packet on the tx+/- lines under the loopback test condition. the loopback function must be independent of the link state. 00: normal operation 01: reserved 10: reserved 11: loopback mode 16 r/w crc append crc: 0: a crc is appended at the end of a packet 1: no crc appended at the end of a packet 15-11 - - reserved 10-8 r/w mxdma2, 1, 0 max dma burst size per tx dma burst: this field sets the maximum size of transmit dma data bursts according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = 2048 bytes www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 16 track id: jatr-1076-21 rev. 1. 6 bit r/w symbol description 7-4 r/w txrr tx retry count: these are used to speci fy additional transmission retries in multiples of 16 (ieee 802.3 csma/cd retry count). if the txrr is set to 0, the transmitter will re-transmit 16 times before aborting due to excessive collisions. if the txrr is set to a value greater than 0, the transmitter will re-transmit a number of times equal to the following formula before aborting: total retries = 16 + (txrr * 16) the ter bit in the isr register or transmit descriptor will be set when the transmission fails and reaches to this specified retry count. 3-1 - - reserved 0 w clrabt clear abort: setting this bit to 1 causes the RTL8139C(l) to retransmit the packet at the last transmitted descriptor when this transmission was aborted. setting this bit is only permitted in the transmit abort state. 6.8. receive configuration register (offset 0044h-0047h, r/w) this register is used to set the receive configuration for the rtl 8139c(l). receive properties su ch as accepting error packets, runt packets, setting the receive drai n threshold etc. are controlled here. bit r/w symbol description 31-28 - - reserved 27-24 r/w erth3, 2, 1, 0 early rx threshold bits: these bits are used to select the rx threshold multiplier of the whole packet that has been transferred to the system buffer in early mode when the frame protocol is under the RTL8139C(l)'s definition. 0000 = no early rx threshold 0001 = 1/16 0010 = 2/16 0011 = 3/16 0100 = 4/16 0101 = 5/16 0110 = 6/16 0111 = 7/16 1000 = 8/16 1001 = 9/16 1010 = 10/16 1011 = 11/16 1100 = 12/16 1101 = 13/16 1110 = 14/16 1111 = 15/16 23-18 - - reserved 17 r/w mulerint multiple early interrupt select: when this bit is set, any received packet invokes early interrupt according to mulint setting in early mode. when this bit is reset, the packets of familiar protocol (ipx, ip, ndis, etc) i nvoke early interrupt according to rcr setting in early mode. the packets of unfamiliar protocol will invoke early interr upt according to the setting of mulint. 16 r/w rer8 the RTL8139C(l) receives the e rror packet whose length is larger than 8 bytes after setting the rer8 bit to 1. the RTL8139C(l) receives the error packet larger than 64-byte long when the rer8 bit is cleared. the power-on default is zero. if aer or ar is set, the rer will be set when the RTL8139C(l) receives an error packet whose length is larger than 8 bytes. the rer8 is ? don?t care ? in this situation. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 17 track id: jatr-1076-21 rev. 1. 6 bit r/w symbol description 15-13 r/w rxfth2, 1, 0 rx fifo threshold: specifies rx fifo threshold level. when the number of the received data byte s from a packet, which is being received into the RTL8139C(l)'s rx fi fo, has reached to this level (or the fifo has contained a complete p acket), the receive pci bus master function will begin to transfer th e data from the fifo to the host memory. this field sets the thres hold level according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = no rx threshold. the RTL8139C(l) begins the transfer of data after having received a whole packet in the fifo. 12-11 r/w rblen1, 0 rx buffer length: this field indicates the size of the rx ring buffer. 00 = 8k + 16 byte 01 = 16k + 16 byte 10 = 32k + 16 byte 11 = 64k + 16 byte 10-8 r/w mxdma2, 1, 0 max dma burst size per rx dma burst: this field sets the maximum size of the receive dma data bursts according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = unlimited 7 r/w wrap 0: the RTL8139C(l) will transfer the rest of the pack et data into the beginning of the rx buffer if this packet has not been completely moved into the rx buffer and the transfer has arrived at the end of the rx buffer. 1: the RTL8139C(l) will keep moving the rest of the packet data into the memory immediately after the end of the rx buffer, if this packet has not been completely moved into the rx buffer and the transfer has arrived at the end of the rx buffer. the software driver must reserve at least 1.5k bytes buffer to accept th e remainder of the packet. we assume that the remainder of the packet is x bytes. the next packet will be moved into the memory from the x byte offset at the top of the rx buffer. this bit is invalid when rx buffer is selected to 64k bytes. 6 r 9356sel eeprom select: this bit reflects what type of eeprom is used. 1: the eeprom used is 9356. 0: the eeprom used is 9346. 5 r/w aer accept error packets: this bit determines if packets with crc error, alignment error and/or collided fragm ents will be accepted or rejected. 0: reject error packets 1: accept error packets www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 18 track id: jatr-1076-21 rev. 1. 6 bit r/w symbol description 4 r/w ar accept runt packets: this bit allows the r eceiver to accept packets that are smaller than 64 bytes. the packet must be at least 8 bytes long to be accepted as a runt. 0: reject runt packets 1: accept runt packets 3 r/w ab accept broadcast packets: this bit allows the receiver to accept or reject broadcast packets. 0: reject broadcast packets 1: accept broadcast packets 2 r/w am accept multicast packets: this bit allows the receiver to accept or reject multicast packets. 0: reject multicast packets 1: accept multicast packets 1 r/w apm accept physical match packets: this bit allows the receiver to accept or reject physical match packets. 0: reject physical match packets 1: accept physical match packets 0 r/w aap accept physical address packets: this bit allows the receiver to accept or reject packets with a physical destination address. 0: reject packets with a physical destination address 1: accept packets with a phy sical destination address www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 19 track id: jatr-1076-21 rev. 1. 6 6.9. 9346cr: 93c46 (93c56) command register (offset 0050h, r/w) bit r/w symbol description 7-6 r/w eem1-0 operating mode: these 2 bits select the RTL8139C(l) operating mode. eem1 eem0 operating mode 0 0 normal (RTL8139C(l) network/host communication mode) 0 1 auto-load: entering this mode will make the RTL8139C(l) load the contents of 93c46 (93c56) as when the rstb signal is asserted. this auto-load operation will take about 2 ms. after it is completed, the RTL8139C(l) goes back to the normal mode automatically (eem1 = eem0 = 0) and all the other registers are reset to default values. 1 0 93c46 (93c56) programming: in this mode, both network and host bus master operations are disabled. the 93c46 (93c56) can be directly acce ssed via bit3-0 which now reflect the states of eecs, eesk, eedi, & eedo pins respectively. 1 1 config register write enab le: before writing to config0, 1, 3, 4 registers, and bit13, 12, 8 of bmcr(offset 62h-63h), the RTL8139C(l) must be placed in this mode. this will prevent RTL8139C(l )'s configurations from accidental change. 4-5 - - reserved 3 r/w eecs 2 r/w eesk 1 r/w eedi 0 r eedo these bits reflect the state of eecs, eesk, eedi & eedo pins in auto-load or 93c46 (93c56) programming mode and are valid only when flash bit is cleared. note: eesk, eedi and eedo is valid after boot rom complete. 6.10. config 0: configuration register 0 (offset 0051h, r/w) bit r/w symbol description 7 r scr scrambler mode: always 0. 6 r pcs pcs mode: always 0. 5 r t10 10 mbps mode: always 0. 4-3 r pl1, pl0 select 10 mbps medium type: always (pl1, pl0) = (1, 0) select boot rom size bs2 bs1 bs0 description 0 0 0 no boot rom 0 0 1 8k boot rom 0 1 0 16k boot rom 0 1 1 32k boot rom 1 0 0 64k boot rom 1 0 1 128k boot rom 1 1 0 unused 1 1 1 unused 2-0 r bs2, bs1, bs0 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 20 track id: jatr-1076-21 rev. 1. 6 6.11. config 1: configuration register 1 (offset 0052h, r/w) bit r/w symbol description 7-6 r/w leds1-0 refer to led pin definition. these bits? initial value come from 93c46/93c56. 5 r/w dvrload driver load: software may use this bit to make sure that the driver has been loaded. writing 1 is 1. writing 0 is 0. when the command register bits ioen, memen, and bmen of the pci c onfiguration space are written, the RTL8139C(l) will clear this bit automatically. lwake active mode: the lwact bit and lwptn bit in the config4 register are used to program the lwake pin?s output signal. according to the combination of these two bits, there may be 4 choices of lwake signal, i.e., active high, active low, positive (high) pulse, and negative (low) pulse. the output pulse width is about 150 ms. in cardbus applications, the lwact and lwptn have no meaning. the default value of each of these two bits is 0, i.e., the default output signal of the lwake pin is an active high signal. lwact lwake output 0 1 0 active high* active low lwptn 1 positive pulse negative pulse 4 r/w lwact * default value. 3 r memmap memory mapping: the operational registers are mapped into pci memory space. 2 r iomap i/o mapping: the operational registers ar e mapped into pci i/o space. 1 r/w vpd vital product data: this is used to set to enable vital product data. the vpd data is stored in 93c46 or 93c56 from within offset 40h-7fh. 0 r/w pmen power management enable: write able only when 93c46cr register eem1=eem0=1 let a denote the new_cap bit (bit 4 of the status register) in the pci configuration space offset 06h. let b denote the cap_ptr register in the pci configuration space offset 34h. let c denote the cap_id (power management) register in the pci configuration space offset 50h. let d denote the power management re gisters in the pci configuration space offset from 52h to 57h. let e denote the next_ptr (power management) register in the pci configuration space offset 51h. pmen description 0 a=b=c=e=0, d not valid 1 a=1, b=50h, c=01h, d valid, e=0 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 21 track id: jatr-1076-21 rev. 1. 6 6.12. media status register (offset 0058h, r/w) this register allows configuration of a variety of de vice and phy options, and provides phy status information. bit r/w symbol description 7 r/w txfce/ ldtxfce tx flow control enable: the flow control is valid in full-duplex mode only. this register?s default value comes from 93c46 (93c56). RTL8139C(l) remote txfce/ldtxfce ane = 1 nway fly mode r/o ane = 1 nway mode only r/w ane = 1 no nway r/w ane = 0 & full-duplex mode - r/w ane = 0 & half-duplex mode - invalid nway fly mode: nway with flow control capability nway mode only: nway without flow control capability 6 r/w rxfce rx flow control enable: the flow control is enabled in full-duplex mode only. the default value comes from 93c46 (93c56). 5 - - reserved 4 r aux_status aux. power present status: 1: the aux. power is present. 0: the aux. power is absent. the value of this bit is fixed after each pci reset. 3 r speed_10 speed: set, when current media is 10 mbps mode. reset, when current media is 100 mbps mode. 2 r linkb inverse of link status: 0 = link ok. 1 = link fail. 1 r txpf transmit pause flag: set when the RTL8139C(l) sends pause packet. reset when the RTL8139C(l) sends timer done packet. 0 r rxpf receive pause flag: set when the RTL8139C(l) is in backoff state because a pause packet received. reset when pause state is clear. 6.13. config 3: configuration register3 (offset 0059h, r/w) bit r/w symbol description 7 r gntsel gnt select: select the frame?s asserted time after the grant signal has been asserted. the frame a nd grant are the pci signals. 1: delay one clock from gnt assertion 0: no delay 6 r/w parm_en parameter enable: (these parameters are used in 100mbps mode) setting to 0 and 9346cr register eem1=eem0=1 enable the phy1_parm, phy2_parm, tw_parm be written via software. setting to 1 will allow parameters auto-loaded from 93c46 (93c56) and disable writing to phy1_parm, phy2_parm and tw_parm registers via software. the phy1_parm, phy2_parm, and tw_parm can be auto-loaded from eeprom in this mode. the parameter auto-load process is ex ecuted every time when the link is ok in 100mbps mode. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 22 track id: jatr-1076-21 rev. 1. 6 bit r/w symbol description 5 r/w magic magic packet: this bit is valid when the pwen bit of config1 register is set. the RTL8139C(l) will assert the pmeb signal to wakeup the operating system when the magic packet is received. once the RTL8139C(l) has been enabled for magic packet wakeup and has been put into adequate st ate, it scans all incoming packets addressed to the node for a specific data sequence, which indicates to the controller that this is a magic packet frame. a magic packet frame must also meet the basic requirements: destination address + source address + data + crc the destination address may be the node id of the receiving station or a multicast address, which includes the broadcast address. the specific sequence consists of 16 duplications of 6 byte id registers, with no breaks or interrupts. this sequence can be located anywhere within the packet, but must be pr eceded by a synchronization stream, 6 bytes of ffh. the device will also accept a multicast address, as long as the 16 duplications of the ieee address ma tch the address of the id registers. if the node id is 11h 22h 33h 44h 55h 66h, then the magic frame?s format is like the following: destination address + source address + misc + ff ff ff ff ff ff + misc + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + misc + crc 4 r/w linkup link up: this bit is valid when the pwen bit of config1 register is set. the RTL8139C(l), in adequate power state, will assert the pmeb signal to wakeup the operating system when the cable connection is re-established. 3 r cardb_en card bus enable: set to 1 to enable cardbus related registers and functions. set to 0 to disable cardbus related registers and functions. 2 r clkrun_en clkrun enable: set to 1 to enable clkrun. set to 0 to disable clkrun. 1 r funcregen functions registers enable (cardbus only): set to 1 to enable the 4 function registers (function event register, function event mask register, function present state register, and function force event register) for cardbus application. set to 0 to disable the 4 function registers for cardbus application. 0 r fbtben fast back to back enable: set to 1 to enable fast back to back. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 23 track id: jatr-1076-21 rev. 1. 6 6.14. config 4: configuration register4 (offset 005ah, r/w) bit r/w symbol description 7 r/w rxfifoautoclr when set to 1, the RTL8139C(l) will clear the rx fifo overflow automatically. 6 r/w anaoff analog power off: this bit can not be auto-loaded from eeprom (9346 or 9356). 1: turn off the analog power of the RTL8139C(l) internally. 0: normal working state. this is also power-on default value. 5 r/w longwf long wake-up frame: the initial value comes from eeprom autoload. set to 1: the RTL8139C(l) suppor ts up to 5 wake-up frames, each with 16-bit crc algorithm for ms wakeup frame, the low byte of 16-bit crc should be placed at th e correspondent crc register, and the high byte of 16-bit crc should be placed at the correspondent lsbcrc register. the wake-up frame 0 and 1 are the same as above, except that the masked bytes start from offset 0 to 63. the wake-up frame 2 and 3 are merged into one long wake-up frame respectively with masked bytes selected from offset 0 to 127. the wake-up frame 4 and 5, 6 and 7 are merged respec tively into another 2 long wake-up frames. please refer to 7.4 pci po wer management functions for a detailed description. set to 0: the RTL8139C(l) supports up to 8 wake-up frames, each with masked bytes selected from offset 12 to 75. 4 r/w lwpme lanwake vs. pmeb: set to 1: the lwake can only be a sserted when the pmeb is asserted and the isolateb is low. set to 0: the lwake and pmeb are asserted at the same time. in cardbus application, this bit has no meaning. 3 - - reserved 2 r/w lwptn lwake pattern: please refer to lwact bit in config1 register. 1 - - reserved 0 r/w pbwakeup pre-boot wakeup: the initial value comes from eeprom autoload. 1: pre-boot wakeup disabled. (suitable for cardbus and minipci application) 0: pre-boot wakeup enabled. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 24 track id: jatr-1076-21 rev. 1. 6 6.15. multiple interrupt select register (offset 005ch-005dh, r/w) if the received packet data is not a fam iliar protocol (ipx, ip, ndis, etc.) to r tl8139c(l), rcr will not be used to transfer data in early mode. this register will be wr itten to the received data length in or der to make an early rx interrup t for the unfamiliar protocol. bit r/w symbol description 15-12 - - reserved 11-0 r/w misr11-0 multiple interrupt select: indicates that the RTL8139C(l) makes an rx interrupt after RTL8139C(l) has transferred the byte data into the system memory. if the value of these bits is zero, there will be no early interrupt as soon as the RTL8139C(l) prepares to execute the first pci transaction of the received data. bit1, 0 must be zero. the erth3-0 bits should not be se t to 0 when the multiple interrupt select register is used. ? the above is true when mulerint=0 (bit17, rcr). when mulerint=1, any r eceived packet invokes early interrupt according to misr[11:0] setting in early mode. 6.16. pci revision id (offset 005eh, r) bit r/w symbol description 7-0 r revision id the value in pci configuration space offset 08h is 10h. 6.17. transmit status of all descriptors (tsad) register (offset 0060h-0061h, r/w) bit r/w symbol description 15 r tok3 tok bit of descriptor 3 14 r tok2 tok bit of descriptor 2 13 r tok1 tok bit of descriptor 1 12 r tok0 tok bit of descriptor 0 11 r tun3 tun bit of descriptor 3 10 r tun2 tun bit of descriptor 2 9 r tun1 tun bit of descriptor 1 8 r tun0 tun bit of descriptor 0 7 r tabt3 tabt bit of descriptor 3 6 r tabt2 tabt bit of descriptor 2 5 r tabt1 tabt bit of descriptor 1 4 r tabt0 tabt bit of descriptor 0 3 r own3 own bit of descriptor 3 2 r own2 own bit of descriptor 2 1 r own1 own bit of descriptor 1 0 r own0 own bit of descriptor 0 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 25 track id: jatr-1076-21 rev. 1. 6 6.18. basic mode control register (offset 0062h-0063h, r/w) bit name description/usage default/ attribute 15 reset this bit sets the status and control registers of the phy(register 0062-0074h) in a default state. this bit is self-clearing. 1 = software reset; 0 = normal operation. 0, rw 14 - reserved - 13 spd_set this bit sets the network speed. 1 = 100mbps; 0 = 10mbps. this bit?s initial value comes from 93c46 (93c56). 0, rw 12 auto negotiation enable (ane) this bit enables/disables the nway auto-negotiation function. set to 1 to enable auto-negotiati on, bit13 will be ignored. set to 0 disables auto-negotiation, bit13 and bit8 will determine the link speed and the data transfer mode, respectively. this bit?s initial value comes from 93c46 (93c56). 0, rw 11-10 - reserved - 9 restart auto negotiation this bit allows the nway auto-negotiation function to be reset. 1 = re-start auto-negotiation; 0 = normal operation. 0, rw 8 duplex mode this bit sets the duplex mode. 1 = full-duplex; 0 = normal operation. this bit?s initial value comes from 93c46 (93c56). if bit12 = 1, read = status write = register value. if bit12 = 0, read = write = register value. 0, rw 7-0 - reserved - 6.19. basic mode status register (offset 0064h-0065h, r) bit name description/usage default/ attribute 15 100base-t4 1 = enable 100base-t4 support; 0 = suppress 100base-t4 support. 0, ro 14 100base_tx_ fd 1 = enable 100base-tx full duplex support; 0 = suppress 100base-tx full duplex support. 1, ro 13 100base_tx_h d 1 = enable 100base-tx half-duplex support; 0 = suppress 100base-tx half-duplex support. 1, ro 12 10base_t_fd 1 = enable 10base-t full duplex support; 0 = suppress 10base-t full duplex support. 1, ro 11 10_base_t_hd 1 = enable 10base-t half-duplex support; 0 = suppress 10base-t half-duplex support. 1, ro 10-6 - reserved - 5 auto negotiation complete 1 = auto-negotiation process completed; 0 = auto-negotiation process not completed. 0, ro 4 remote fault 1 = remote fault condition detected (cleared on read); 0 = no remote fault condition detected. 0, ro 3 auto negotiation 1 = link had not been experienced fail state. 0 = link had been experienced fail state 1, rd 2 link status 1 = valid link established; 0 = no valid link established. 0, ro 1 jabber detect 1 = jabber condition detected; 0 = no jabber condition detected. 0, ro 0 extended capability 1 = extended register capability; 0 = basic register capability only. 1, ro www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 26 track id: jatr-1076-21 rev. 1. 6 6.20. auto-negotiation advertisement register (offset 0066h-0067h, r/w) bit name description/usage default/ attribute 15 np next page bit. 1 = transmitting the protocol specific data page; 0 = transmitting the primary capability data page 0, ro 14 ack 1 = acknowledge reception of link part ner capability data word. 0, ro 13 rf 1 = advertise remote fault detection capability; 0 = do not advertise remote fault detection capability. 0, rw 12-11 - reserved - 10 pause 1 = flow control is supported by local node. 0 = flow control is not supported by local mode. the default value comes from eeprom, ro 9 t4 1 = 100base-t4 is supported by local node; 0 = 100base-t4 not supported by local node. 0, ro 8 txfd 1 = 100base-tx full duplex is supported by local node; 0 = 100base-tx full duplex not supported by local node. 1, rw 7 tx 1 = 100base-tx is supported by local node; 0 = 100base-tx not supported by local node. 1, rw 6 10fd 1 = 10base-t full duplex supported by local node; 0 = 10base-t full duplex not supported by local node. 1, rw 5 10 1 = 10base-t is supported by local node; 0 = 10base-t not supported by local node. 1, rw 4-0 selector binary encoded selector supported by this node. currently only csma/ cd <00001> is specified. no other protocols are supported. <00001>, rw www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 27 track id: jatr-1076-21 rev. 1. 6 6.21. auto-negotiation link partner ability register (offset 0068h-0069h, r) bit name description/usage default/ attribute 15 np next page bit. 1 = transmitting the protocol specific data page; 0 = transmitting the primary capability data page 0, ro 14 ack 1 = link partner acknowledges recep tion of local node?s capability data word. 0, ro 13 rf 1 = link partner is indicating a remote fault. 0, ro 12-11 - reserved - 10 pause 1 = flow control is supported by link partner, 0 = flow control is not supported by link partner. 0, ro 9 t4 1 = 100base-t4 is supported by link partner; 0 = 100base-t4 not supported by link partner. 0, ro 8 txfd 1 = 100base-tx full duplex is supported by link partner; 0 = 100base-tx full duplex not supported by link partner. 0, ro 7 tx 1 = 100base-tx is supported by link partner; 0 = 100base-tx not supported by link partner. 0, ro 6 10fd 1 = 10base-t full duplex is supported by link partner; 0 = 10base-t full duplex not supported by link partner. 0, ro 5 10 1 = 10base-t is supported by link partner; 0 = 10base-t not supported by link partner. 0, ro 4-0 selector link partner's binary encoded node selector. currently only csma/ cd <00001> is specified. <00000>, ro 6.22. auto-negotiation expansion register (offset 006ah-006bh, r) this register contains additional status for nway auto-negotiation. bit name description/usage default/ attribute 15-5 - reserved. these bits are always set to 0. - 4 mlf status indicating if a multiple link fault has occurred. 1 = fault occurred; 0 = no fault occurred. 0, ro 3 lp_np_able status indicating if the link partne r supports next page negotiation. 1 = supported; 0 = not supported. 0, ro 2 np_able this bit indicates if the local node is able to send additional next pages. 0, ro 1 page_rx this bit is set when a new link code word page has been received. the bit is automatically cleared when the auto-negotiation link partner?s ability register (register 5) is read by management. 0, ro 0 lp_nw_able 1 = link partner supports nway auto-negotiation. 0, ro 6.23. disconnect counter (offset 006ch-006dh, r) bit name description/usage default/ attribute 15-0 dcnt this 16-bit counter increments by 1 for every disconnect event. it rolls over when becomes full. it is cl eared to zero by read command. h'[0000], r www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 28 track id: jatr-1076-21 rev. 1. 6 6.24. false carrier sense counter (offset 006eh-006fh, r) this counter provides information required to implement the ?fal se carriers? attribute within the mau managed object class of clause 30 of the ieee 802.3u specification. bit name description/usage default/ attribute 15-0 fcscnt this 16-bit counter increments by 1 for each false carrier event. it is cleared to zero by read command. h'[0000], r 6.25. nway test register (offset 0070h-0071h, r/w) bit name description/usage default/ attribute 15-8 - reserved - 7 nwlpbk 1 = set nway to loopback mode. 0, rw 6-4 - reserved - 3 ennwle 1 = led0 pin indicates linkpulse 0, rw 2 flagabd 1 = auto-neg experienced ability detect state 0, ro 1 flagpdf 1 = auto-neg experienced parallel detection fault state 0, ro 0 flaglsc 1 = auto-neg experienced link status check state 0, ro 6.26. rx_er counter (offset 0072h-0073h, r) bit name description/usage default/ attribute 15-0 rxercnt this 16-bit counter increments by 1 for each valid packet received. it is cleared to zero by read command. h'[0000], r 6.27. cs configuration register (offset 0074h-0075h, r/w) bit name description/usage default/ attribute 15 testfun 1 = auto-neg speeds up internal timer 0,wo 14-10 - reserved - 9 ld active low tpi link disable signal. when low, tpi still transmits link pulses and tpi stays in good link state. 1, rw 8 heart beat 1 = heart beat enable, 0 = heart beat disable. heart beat function is only valid in 10mbps mode. 1, rw 7 jben 1 = enable jabber function. 0 = disable jabber function 1, rw 6 f_link_100 used to login force good link in 100mbps for diagnostic purposes. 1 = disable, 0 = enable. 1, rw 5 f_connect assertion of this bit forces the disconnect function to be bypassed. 0, rw 4 - reserved - 3 con_status this bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. 0, ro 2 con_status_en assertion of this bit configures led1 pin to indicate connection status. 0, rw 1 - reserved - 0 pass_scr bypass scramble 0, rw www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 29 track id: jatr-1076-21 rev. 1. 6 6.28. flash memory read/write register (offset 00d4h-00d7h, r/w) bit r/w symbol description 31-24 r/w md7-md0 flash memory data bus: these bits set and reflect the state of the md7 - md0 pins, during write and read process respectively. 23-21 - - reserved 20 w romcsb chip select: this bit sets the state of the romcsb pin. 19 w oeb output enable: this bit sets the state of the oeb pin. 18 w web write enable: this bit sets the state of the web pin. 17 w swrwen enable software access to flash memory: 0: disable read/write access to flash memory via software. 1: enable read/write access to flas h memory via soft ware and disable the eeprom access during flash memory access via software. 16-0 w ma16-ma0 flash memory address bus: these bits set the state of the ma16-0 pins. 6.29. config5: configuration register 5 (offset 00d8h, r/w) this register, unlike other config registers, is not protected by the 93c46 command register. therefore, there is no need to enable config register write prior to writing to config5. bit r/w symbol description 7 - - reserved 6 r/w bwf broadcast wakeup frame: 0: default value. disable broadcast wakeup frame with mask bytes of only did field = ff ff ff ff ff ff. 1: enable broadcast wakeup frame with mask bytes of only did field = ff ff ff ff ff ff. the power-on default value of this bit is 0. 5 r/w mwf mroadcast wakeup frame: 0: default value. disable multicast wakeup frame with mask bytes of only did field, which is a multicast address. 1: enable multicast wakeup frame with mask bytes of only did field, which is a multicast address. the power-on default value of this bit is 0. 4 r/w uwf unicast wakeup frame: 0: default value. disable unicast wakeup frame with mask bytes of only did field, which is its own physical address. 1: enable unicast wakeup frame with mask bytes of only did field, which is its own physical address. the power-on default value of this bit is 0. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 30 track id: jatr-1076-21 rev. 1. 6 bit r/w symbol description 3 r/w fifoaddrptr fifo address pointer: (realtek internal use only to test fifo sram) 0: (power-on) default value. both rx and tx fifo address pointers are updated in ascending way from 0 and upwards. the initial fifo address pointer is 0. 1: both rx and tx fifo address pointers are updated in descending way from 1ffh and downwards. the initial fifo address pointer is 1ffh. note: this bit does not participate in eeprom auto-load. the fifo address pointers can not be reset, except initial power-on. the power-on default value of this bit is 0. 2 r/w ldps link down power saving mode: when cable is disconnected (link down), the analog part will power down itself (phy tx part & part of twister) automatically. however, the phy rx part and part of twister to monitor sd signal will not, in case the cable is re-connected and link should be established again. 1: disable. 0: enable. 1 r/w lanwake lanwake signal enable/disable: 1: enable lanwake signal. 0: disable lanwake signal. 0 r/w pme_sts pme_status bit: always sticky/can be reset by pci rst# and software. 1: the pme_status bit can be reset by pci reset or by software. 0: the pme_status bit can only be reset by software. ? config5 register, offset d8h: (sym_err register is changed to config5, the function of sym_err register is no longer supported by RTL8139C.) ? the 3 bits (bit2-0) are auto-loaded from eeprom config5 byte to RTL8139C config5 register. 6.30. function event register (offset 00f0h-00f3h, r/w) bit r/w symbol description 31-16 - - reserved 15 r/w intr interrupt: this bit is set to 1 when intr field in the function force event register is set. writing a 1 may clear this bit. writing a 0 has no effect. this bit is not affected by the rst# pin and software reset. 14-5 - - reserved 4 r/w gwake general wakeup: this bit is set to 1 when the gwake field in the function present state register change s its state from 0 to 1. this bit can also be set when the gwake bit of the function force register is set. writing a 1 may clear this bit. writing a 0 has no effect. this bit is not affected by the rst# pin. 3-0 - - reserved ? this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). ? the function event (offset f0h), function event mask (offset f4h), function present state (offset f8h), and function force event (offset fch) registers have some corresponding fields with the same names. the gwake and intr bits of these registers reflect the wake-up event signaled on the sctcschg pin. the operation of cstcschg pin is similar to pme# pin except that the cstcschg pin is asserted high. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 31 track id: jatr-1076-21 rev. 1. 6 6.31. function event mask register (offset 00f4h-00f7h, r/w) bit r/w symbol description 31-16 - - reserved 15 r/w intr interrupt mask: when cleared (0), setting of the intr bit in either the function present state register or the function event register will neither cause assertion of the int# signal while the cardbus pc card interface is powered up, nor the system wakeup (cstschg) while the interface is powered off. setting this bit to 1, enables the intr bit in both the function present state register and the function event register to generate the int# signal (and the system wakeup if the corresponding wkup field in this function event mask register is also set). this bit is not affected by the rst# pin. 14 r/w wkup wakeup mask: when cleared (0), the wakeup function is disabled, i.e., the setting of this bit in the function event register will not assert the cstschg signal. setting this bit to 1, enables the fields in the function event register to assert the cstschg signal. this bit is not affected by rst#. 13-5 - - reserved 4 r/w gwake general wakeup mask: when cleared (0), setting this bit in the function event register will not cause the cstschg pin to be asserted. setting this bit to 1, enables the gwake field in the function event register to assert cstschg pin if bit14 of this register is also set. this bit is not affected by rst#. 3-0 - - reserved ? this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). 6.32. function present state register (offset 00f8h-00fbh, r) bit r/w symbol description 31-16 - - reserved 15 r intr interrupt: this bit is set when one of the isr register bits has been set to 1. this bit remains set (1), until all of the isr register bits have been cleared. it is not affected by rst#. 14-5 - - reserved 4 r gwake general wakeup: this bit reflects the current state of the wakeup event(s), it?s just like the pme_status bit of the pmcsr register. this bit remains set (1), until the pme_status bit of the pmcsr register is cleared. it is not affected by rst#. 3-0 - - reserved ? this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). ? this read-only register reflects th e current state of the function. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 32 track id: jatr-1076-21 rev. 1. 6 6.33. function force event register (offset 00fch-00ffh, w) bit r/w symbol description 31-16 - - reserved 15 w intr interrupt: writing a 1 sets the intr bit in the function event register. however, the intr b it in the function present state register is not affected and continue s to reflect the current state of the isr register. writing a 0 to this bit has no effect. 14-5 - - reserved 4 w gwake general wakeup: setting this bit to 1, sets the gwake bit in the function event register. however, the gwake bit in the function present state register is not affected and continues to reflect the current state of the wakeup request. writing a 0 to this bit has no effect. 3-0 - - reserved ? this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 33 track id: jatr-1076-21 rev. 1. 6 7. eeprom contents (93c46 or 93c56) the 93c46 is a 1k-bit eeprom (the 93c56 is a 2k-bit eeprom). although it is actually addressed by words, its contents are listed below by bytes for convenience. after the valid duration of the rstb pin or auto-load command in 9346cr, the RTL8139C(l) performs a series of eeprom read opera tions from the 93c46 (93c56) address 00h to 31h. ? it is recommended to obtain realtek approval befo re changing the default settings of the eeprom. bytes contents description 00h 29h 01h 81h these 2 bytes contain the id code word for the RTL8139C(l). the RTL8139C(l) will load the contents of the eeprom into the corresponding location if the id word (8129h) is correct, otherwise, the vendor id and de vice id of the pci configuration space are hex 10ec and 8129 respectively. 02h-03h vid pci vendor id, pci conf iguration space offset 00h-01h. 04h-05h did pci device id, pci conf iguration space offset 02h-03h. 06h-07h svid pci subsystem vendor id, pci configuration space offset 2ch-2dh. 08h-09h smid pci subsystem id, pci c onfiguration space offset 2eh-2fh. 0ah mngnt pci minimum grant timer, pci configuration space offset 3eh. 0bh mxlat pci maximum latency timer, pci configuration space offset 3fh. 0ch msrbmcr bits 7-6 map to bits 7-6 of the media status register (msr); bits 5, 4, 0 map to bits 13, 12, 8 of the basic mode control register (bmcr); bits 3-2 are reserved. if the network speed is set to auto-detect mode (i.e. nway mode), then bit 1=0 means the local RTL8139C(l) supports flow c ontrol (ieee 802.3x). in this case, bit 10=1 in the auto-negotiation advertisement register (offset 66h-67h). bit 1=1 means the local RTL8139C(l) does not support flow control. in this case, bit 10=0 in auto-negotiation advertisement. this is b ecause there are nway switch hubs which keep sending flow control pause packets for no reason, if the link partner supports nway flow control. 0dh config3 RTL8139C(l) configuration regist er 3, operational register offset 59h. 0eh-13h ethernet id after auto-load command or hardware reset, the RTL8139C(l) loads the ethernet id to idr0-idr5 of the RTL8139C(l)'s i/o registers. 14h config0 RTL8139C(l) configuration regist er 0, operational registers offset 51h. 15h config1 RTL8139C(l) configuration regist er 1, operational registers offset 52h. 16h-17h pmc reserved. do not change this field without realtek approval. power management capabilities. pci c onfiguration space address 52h and 53h. 18h - reserved. do not change this field without realtek approval. 19h config4 reserved. do not change this field without realtek approval. RTL8139C(l) configuration register 4, operational registers offset 5ah. 1ah-1dh phy1_parm_u reserved. do not change this field without realtek approval. phy parameter 1-u for RTL8139C. operational registers of the RTL8139C(l) are from 78h to 7bh. 1eh phy2_parm_u reserved. do not change this field without realtek approval. phy parameter 2-u for RTL8139C. operational register of the RTL8139C(l) is 80h. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 34 track id: jatr-1076-21 rev. 1. 6 bytes contents description 1fh config_5 do not change this field without realtek approval. bit7-3: reserved. bit2: link down power saving mode: set to 1: disable. set to 0: enable. when cable is disconnected(link down), the analog part will power down itself (phy tx part & part of twister) automatically except phy rx part and part of twister to monitor sd signal in case that cable is re-connected and link should be established again. bit1: lanwake signal enable/disable set to 1: enable lanwake signal. set to 0: disable lanwake signal. bit0: pme_status bit property set to 1: the pme_status bit can be reset by pci reset or by software if d3cold_support_pme is 0. if d3cold_support_pme=1, the pme_status bit is a sticky bit. set to 0: the pme_status bit is always a sticky bit and can only be reset by software. 20h-23h tw_parm_u reserved. do not change this field without realtek approval. twister parameter u for RTL8139C. operational registers of the RTL8139C(l) are 7ch-7fh. 24h-27h tw_parm_t reserved. do not change this field without realtek approval. twister parameter t for RTL8139C. operational registers of the RTL8139C(l) are 7ch-7fh. 28h-2bh phy1_parm_t reserved. do not change this field without realtek approval. phy parameter 1-t for RTL8139C. operational registers of the RTL8139C(l) are from 78h to 7bh. 2ch phy2_parm_t reserved. do not change this field without realtek approval. phy parameter 2-t for RTL8139C. operational register of the RTL8139C(l) is 80h. 2dh-2fh - reserved. 30h-31h cispointer reserved. do not change this field without realtek approval. cis pointer. 32h-33h checksum reserved. do not change this field without realtek approval. checksum of the eeprom content. 34h-3eh - reserved. do not change this field without realtek approval. 3fh pxe_para reserved. do not change this field without realtek approval. pxe rom code parameter. 40h-7fh vpd_data vpd data field. offset 40h is the start address of the vpd data. 80h-ffh cis_data cis data field. offset 80h is the start address of the cis data. (93c56 only). www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 35 track id: jatr-1076-21 rev. 1. 6 7.1. summary of eeprom registers offset name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h-05h idr0 ? idr5 r/w* 51h config0 r - - - - bs2 bs1 bs0 w * - - - - - - - - 52h config1 r leds1 leds0 dvrload lwact memmap iomap vpd pmen w * leds1 leds0 dvrload lwact - - vpd pmen 58h r txfce rxfce - - - - w * txfce rxfce - - - - 63h r - - spd_set ane - - - fudup msrbmcr w * - - spd_set ane - - - fudup 59h config3 r gntdel parm_en magic linkup cardb_en clkru n_en funcreg en fbtben w * - parm_en magic linkup - - - - 5ah config4 r/w *rxfifo autoclr anaoff longwf lwpme - lwptn - - 78h-7bh phy1_parm r/w ** 32 bit read write 7ch-7fh tw1_parm tw2_parm r/w ** 32 bit read write 32 bit read write 80h phy2_parm r/w ** 8 bit read write * the registers marked with type = w * can be written only if bits eem1=eem0=1. ** the registers marked with type = w ** can be written only if bits eem1=eem0=1 and config3 = 0. 7.2. summary of eeprom power management registers configuration space offset name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 52h r aux_i_b1 aux_i_b0 dsi reserved pmeclk version 53h pmc r pme_d3 cold pme_d3 ho t pme_d2 pme_d1 pme_d0 d2 d1 aux_i_b2 r pme_status - - - - - - pme_en 55h pmcs r w pme_status - - - - - - pme_en www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 36 track id: jatr-1076-21 rev. 1. 6 8. pci configuration space registers 8.1. pci configuration space table no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h vid r vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 01h r vid15 vid14 vid13 vid12 vid11 vid10 vid9 vid8 02h did r did7 did6 did5 did4 did3 did2 did1 did0 03h r did15 did14 did13 did12 did11 did10 did9 did8 04h command r 0 perrsp 0 0 - bmen memen ioen w - perrsp - - - bmen memen ioen 05h r 0 0 0 0 0 0 fbtben serren w - - - - - - - serren 06h status r fbbc 0 0 newcap 0 0 0 0 07h r dperr sserr rmabt rtabt stabt dst1 dst0 dpd w dperr sserr rmabt rtabt stabt - - dpd 08h revision id r 0 0 0 0 0 0 0 0 09h pifr r 0 0 0 0 0 0 0 0 0ah scr r 0 0 0 0 0 0 0 0 0bh bcr r 0 0 0 0 0 0 1 0 0ch cls r 0 0 0 0 0 0 0 0 0dh ltr r ltr7 ltr6 ltr5 ltr4 ltr3 ltp2 ltr1 ltr0 w ltr7 ltr6 ltr5 ltr 4 ltr3 ltp2 ltr1 ltr0 0eh htr r 0 0 0 0 0 0 0 0 0fh bist r 0 0 0 0 0 0 0 0 10h ioar r 0 0 0 0 0 0 0 ioin w - - - - - - - - 11h r/w ioar15 ioar14 ioar13 ioar12 ioar11 ioar10 ioar9 ioar8 12h r/w ioar23 ioar22 ioar21 ioar20 ioar19 ioar18 ioar17 ioar16 13h r/w ioar31 ioar30 ioar29 ioar28 ioar27 ioar26 ioar25 ioar24 14h memar r 0 0 0 0 0 0 0 memin w - - - - - - - - 15h r/w mem15 mem14 mem13 mem12 mem11 mem10 mem9 mem8 16h r/w mem23 mem22 mem21 mem20 mem19 mem18 mem17 mem16 17h r/w mem31 mem30 mem29 mem28 mem27 mem26 mem25 mem24 18h-2 7h reserved 28h-2 bh cisptr cardbus cis pointer 2ch svid r svid7 svid6 svid5 svid4 svid3 svid2 svid1 svid0 2dh r svid15 svid14 svid13 svid12 svid11 svid10 svid9 svid8 2eh smid r smid7 smid6 smid5 smid4 smid3 smid2 smid1 smid0 2fh r smid15 smid14 smid13 smid12 smid11 smid10 smid9 smid8 30h bmar r 0 0 0 0 0 0 0 bromen w - - - - - - - bromen 31h r bmar15 bmar14 bmar13 bmar12 bmar11 0 0 0 w bmar15 bmar14 bmar13 bmar12 bmar11 - - - 32h r/w bmar23 bmar22 bmar21 bmar20 bmar19 bmar18 bmar17 bmar16 33h r/w bmar31 bmar30 bmar29 bmar28 bmar27 bmar26 bmar25 bmar24 34h cap_ptr r 0 1 0 1 0 0 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 37 track id: jatr-1076-21 rev. 1. 6 no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 35h-3 bh reserved 3ch ilr r/w irl7 ilr6 ilr5 ilr4 ilr3 ilr2 ilr1 ilr0 3dh ipr r 0 0 0 0 0 0 0 1 3eh mngnt r 0 0 1 0 0 0 0 0 3fh mxlat r 0 0 1 0 0 0 0 0 40h? 4fh reserved 50h pmid r 0 0 0 0 0 0 0 1 51h nextptr r 0 0 0 0 0 0 0 0 52h pmc r aux_i_b1 aux_i_b0 dsi reserved pmeclk version 53h r pme_d3 cold pme_d3 hot pme_d2 pme_d1 pme_d0 d2 d1 aux_i_b2 54h pmcsr r 0 0 0 0 0 0 power state w - - - - - - power state 55h r pme_status - - - - - - pme_en w pme_status - - - - - - pme_en 56h? 5fh reserved 60h vpdid r 0 0 0 0 0 0 1 1 61h nextptr r 0 0 0 0 0 0 0 0 62h flag vpd address r/w vpdaddr 7 vpdaddr 6 vpdadd r5 vpdadd r4 vpdadd r3 vpdadd r2 vpdadd r1 vpdadd r0 63h r/w flag vpdaddr 14 vpdadd r13 vpdadd r12 vpdadd r11 vpdadd r10 vpdadd r9 vpdadd r8 64h r/w data7 data6 data5 data 4 data3 data2 data1 data0 65h r/w data15 data14 data13 data 12 data11 data10 data9 data8 66h r/w data23 data22 data21 data 20 data19 data18 data17 data16 67h vpd data r/w data31 data30 data29 data 28 data27 data26 data25 data24 68h-f fh reserved www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 38 track id: jatr-1076-21 rev. 1. 6 8.2. pci configuration space functions the pci configuration space is intended for configuration, initialization, and catastrophic error handling functions. the functions of RTL8139C(l)'s confi guration space are described below. vid: vendor id. this field will be set to a value corresponding to pci vendor id in the external eeprom. if there is no eeprom, this field will default to a value of 10e ch which is realtek semiconductor's pci vendor id. did: device id. this field will be set to a value corresponding to pci device id in the external eeprom. if there is no eeprom, this field will default to a value of 8129h. command: the command register is a 16-bit register used to provide coarse control over a device's ability to generate and respond to pci cycles. bit symbol description 15-10 - reserved 9 fbtben fast back-to-back enable: config3=0:read as 0. write operation has no effect. the RTL8139C(l) will not generate fa st back-to-back cycles. wh en config3=1, this read/write bit controls whether or not a master can do fast back-to-back transactions to different devices. initialization software will set the bit if all targets are fast back-to-back capable. a value of 1 means the master is allowed to generate fast back-t o-back transaction to different agents. a value of 0 means fast back-to-back transactions are only allowed to the same agent. this bit?s state after rst# is 0. 8 serren system error enable: when set to 1, the RTL8139C(l) asserts the serrb pin when it detects a parity error on the address phase (ad<31:0> and cbeb<3:0> ). 7 adstep address/data stepping: read as 0, write operation has no effect. the RTL8139C(l) never performs address/data stepping. 6 perrsp parity error response: when set to 1, RTL8139C(l) will asse rt the perrb pin on the detection of a data parity error when acting as the target, and will sample the perrb pin as the master. when set to 0, any detected parity error is ignored a nd the RTL8139C(l) continues normal operation. parity checking is disabled after hardware reset (rstb). 5 vgasnoo p vga palette snoop: read as 0, write operation has no effect. 4 mwien memory write and invalidate cycle enable: read as 0, write operation has no effect. 3 scycen special cycle enable: read as 0, write operation has no effect. the RTL8139C(l) ignores all special cycle operation. 2 bmen bus master enable: when set to 1, the RTL8139C(l) is capable of acting as a bus master. when set to 0, it is prohibited from acting as a pci bus master. for the normal operation, this bit must be set by the system bios. 1 memen memory space access: when set to 1, the RTL8139C(l) responds to memory space accesses. when set to 0, the RTL8139C(l) ignores memory space accesses. 0 ioen i/o space access: when set to 1, the RTL8139C(l) responds to io space access. when set to 0, the RTL8139C(l) ignores i/o space accesses. status: the status register is a 16-bit register us ed to record status information for pci bus related events. reads to this register behave normally. writes are slightly different in that bits can be reset, but not set. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 39 track id: jatr-1076-21 rev. 1. 6 bit symbol description 15 dperr detected parity error: when set indicates that the RTL8139C(l) detected a parity error, even if parity error handling is disabled in command register perrsp bit. 14 sserr signaled system error: when set indicates that the RTL8139C(l) asserted the system error pin, serrb. writing a 1 clears this bit to 0. 13 rmabt received master abort: when set indicates that the RTL8139C(l) terminated a master transaction with master abort. writing a 1 clears this bit to 0. 12 rtabt received target abort: when set indicates that the RTL8139C(l) master transaction was terminated due to a target abort. writing a 1 clears this bit to 0. 11 stabt signaled target abort : set to 1 whenever the RTL8139C(l) terminates a transaction with target abort. writing a 1 clears this bit to 0. 10-9 dst1-0 device select timing: these bits encode the timing of devselb. they are set to 01b (medium), indicating the RTL8139C(l) will assert devselb two clocks after frameb is asserted. 8 dpd data parity error detected: this bit sets when the following conditions are met: ? the RTL8139C(l) asserts parity error(perrb pin) or it senses the assertion of perrb pin by another device. ? the RTL8139C(l) operates as a bus master for the operation that caused the error. ? the command register perrsp bit is set. writing a 1 clears this bit to 0. 7 fbbc fast back-to-back capable: config3=0, read as 0, write operation has no effect. config3=1, read as 1. 6 udf user definable features supported: read as 0, write operation has no effect. the RTL8139C(l) does not support udf. 5 66mhz 66 mhz capable: read as 0, write operation has no effect. the RTL8139C(l) has no 66mhz capability. 4 newcap new capability: config3=0, read as 0, write operation has no effect. config3=1, read as 1. 0-3 - reserved rid: revision id register the revision id register is an 8-bit register that specifies the RTL8139C(l) controller revision number. pifr: programming interface register the programming interface register is an 8-bit register that id entifies the programming interface of the RTL8139C(l) controller. because the pci version 2.1 specification does not define any specific value for network devices, pifr = 00h. scr: sub-class register the sub-class register is an 8-bit register that identifies the function of the RTL8139C(l). scr = 00h indicates that the RTL8139C(l) is an ethernet controller. bcr: base-class register the base-class register is an 8-bit regi ster that broadly classifies the func tion of the RTL8139C(l). bcr = 02h indicates that the RTL8139C(l) is a network controller. cls: cache line size reads will return a 0, writes are ignored. ltr: latency timer register specifies, in units of pci bus clocks, the value of the latency timer of the RTL8139C(l). when the RTL8139C(l) asserts frameb, it enables its latency timer to count. if the RTL8139C(l) deasserts frameb prior to count expiration, the content of the latency timer is ignored. otherwise, after the count expires, the RTL8139C(l) initiates transaction termination as soon as its gntb is deasserted . software is able to read or write, and the default value i s 00h. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 40 track id: jatr-1076-21 rev. 1. 6 htr: header type register reads will return a 0, writes are ignored. bist: built-in self test reads will return a 0, writes are ignored. ioar: this register specifies the base io a ddress which is required to build an address map during configuration. it also specifies the number of bytes required as well as an indication that it can be mapped into io space. bit symbol description 31-8 ioar31-8 base io address: this is set by software to the base io address for the operational register map. 7-2 iosize size indication: read back as 0. this allows the pci bridge to determine that the RTL8139C(l) requires 256 bytes of io space. 1 - reserved 0 ioin io space indicator: read only. set to 1 by the RTL8139C(l) to indicate that it is capable of being mapped into io space. memar: this register specifies the base memo ry address for memory accesses to the RTL8139C(l) operational registers. this register must be initialized prior to accessing any of the RTL8139C(l)'s register with memory access. bit symbol description 31-8 mem31-8 base memory address: this is set by software to the base address for the operational register map. 7-4 memsize memory size: these bits return 0, which indicates that the RTL8139C(l) requires 256 bytes of memory space. 3 mempf memory prefetchable: read only. set to 0 by the RTL8139C(l). 2-1 memloc memory location select: read only. set to 0 by the RTL8139C(l). this indicates that the base register is 32-bit wide and can be placed anywhere in the 32-bit memory space. 0 memin memory space indicator: read only. set to 0 by the RTL8139C(l) to indicate that it is capable of being mapped into memory space. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 41 track id: jatr-1076-21 rev. 1. 6 cisptr: cardbus cis pointer. this field is valid only when cardb_en (bit3, config3) = 1. the value of this register is auto-loaded from 93c46 or 93c56 (from offset 30h-31h). - bit 2-0: address space indicator bit2-0 meaning 0 not supported. (cis begins in de vice-dependent conf iguration space.) 1-6 the cis begins in the memory address governed by one of the six base address registers. ex., if the value is 2, then the cis begins in the memory address space governed by ba se address register 2. 7 the cis begins in the expansion rom space. - bit27-3: address space offset - bit31-28: rom image number bit2-0 space type address space offset values 0 configuration space not supported. x; 1 x 6 memory space 0h value ffff fff8h. this is the offset into the memory address space governed by base address register x. adding this value to the value in the base address register gives the location of the start of the cis. for RTL8139C(l), the value is 100h. 7 expansion rom 0 image number fh, 0h value 0fff fff8h. this is the offset into the expansion rom address space governed by the expansion rom base register. the image number is in the uppermost nibble of the cisptr register. the value consists of the remaining bytes. for RTL8139C(l), the image number is 0h. this read-only register points to where th e cis begins, in one of the following spaces: i. memory space --- the cis may be in any of the memory spaces from offset 100h and up after being auto-loaded from 93c56. the cis is stored in 93c56 eeprom physically from offset 80h-ffh. ii. expansion rom space --- the cis is stored in e xpansion rom physically within the 128kb max. svid: subsystem vendor id. this field will be set to a value co rresponding to the pci subsystem vendor id in the external eeprom. if there is no eeprom, this fi eld will default to a value of 11ech which is realtek semiconductor's pci subsystem vendor id. smid: subsystem id. this field will be set to a value corresponding to the pci subsystem id in the external eeprom. if there is no eeprom, this field will default to a value of 8129h. bmar: this register specifies the base memo ry address for memory accesses to the r tl8139c(l) operational registers. this register must be initialized prior to accessing any of the RTL8139C(l)'s registers with memory access. bit symbol description 31-18 bmar31-18 boot rom base address 17-11 romsize these bits indicate how ma ny boot rom spaces to be supported. the relationship between config 0 and bmar17-11 is the following: bs2 bs1 bs0 description 0 0 0 no boot rom, bromen=0 (r) 0 0 1 8k boot rom, bromen (r/w), bmar12-11 = 0 (r), bmar17-13 (r/w) 0 1 0 16k boot rom, bromen (r/w), bmar13-11 = 0 (r), bmar17-14 (r/w) 0 1 1 32k boot rom, bromen (r/w), bmar14-11 = 0 (r), bmar17-15 (r/w) 1 0 0 64k boot rom, bromen (r/w), bmar15-11 = 0 (r), bmar17-16 (r/w) 1 0 1 128k boot rom, bromen(r/w), bmar16-11=0 (r), bmar17 (r/w) 1 1 0 unused 1 1 1 unused 10-1 - reserved (read back 0) 0 bromen boot rom enable: this is used by th e pci bios to enable accesses to boot rom. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 42 track id: jatr-1076-21 rev. 1. 6 ilr: interrupt line register the interrupt line register is an 8-bit register used to co mmunicate with the routing of the interrupt. it is written by the post software to set interrupt line for the RTL8139C(l). ipr: interrupt pin register the interrupt pin register is an 8-bit register indicating the interrupt pin used by the RTL8139C(l). the RTL8139C(l) uses inta interrupt pin. read only. ipr = 01h. mngnt: minimum grant timer: read only specifies how long a burst period the RTL8139C(l) needs at 33 mhz clock rate in units of 1/4 microsecond. this field will be set to a value from the exte rnal eeprom. if there is no eeprom, this field will default to a value of 20h. mxlat: maximum latency timer: read only specifies how often the RTL8139C(l) needs to gain access to the pci bus in units of 1/4 microseconds. this field will be set to a value from th e external eeprom. if there is no eeprom, this field will default to a value of 20h. 8.3. default values after power-on (rstb asserted) 8.3.1. pci configuration space table no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h vid r 1 1 1 0 1 1 0 0 01h r 0 0 0 1 0 0 0 0 02h did r 0 0 1 0 1 0 0 1 03h r 1 0 0 0 0 0 0 1 04h command r 0 0 0 0 0 0 0 0 w - perrsp - - - bmen memen ioen 05h r 0 0 0 0 0 0 0 0 w - - - - - - - serren 06h status r 0 0 0 newcap 0 0 0 0 07h r 0 0 0 0 0 0 1 0 w dperr sserr rmabt rtabt stabt - - dpd 08h revision id r 0 0 0 0 0 0 0 0 09h pifr r 0 0 0 0 0 0 0 0 0ah scr r 0 0 0 0 0 0 0 0 0bh bcr r 0 0 0 0 0 0 1 0 0ch cls r 0 0 0 0 0 0 0 0 0dh ltr r 0 0 0 0 0 0 0 0 w ltr7 ltr6 ltr5 ltr 4 ltr3 ltp2 ltr1 ltr0 0eh htr r 0 0 0 0 0 0 0 0 0fh bist r 0 0 0 0 0 0 0 0 10h ioar r 0 0 0 0 0 0 0 1 11h r/w 0 0 0 0 0 0 0 0 12h r/w 0 0 0 0 0 0 0 0 13h r/w 0 0 0 0 0 0 0 0 14h memar r 0 0 0 0 0 0 0 0 15h r/w 0 0 0 0 0 0 0 0 16h r/w 0 0 0 0 0 0 0 0 17h r/w 0 0 0 0 0 0 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 43 track id: jatr-1076-21 rev. 1. 6 no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 18h | 27h - reserved(all 0) 28h r 0 0 0 0 0 0 0 0 29h r 0 0 0 0 0 0 0 0 2ah r 0 0 0 0 0 0 0 0 2bh cisptr r 0 0 0 0 0 0 0 0 2ch svid r 1 1 1 0 1 1 0 0 2dh r 0 0 0 1 0 0 0 1 2eh smid r 0 0 1 0 1 0 0 1 2fh r 1 0 0 0 0 0 0 1 30h bmar r 0 0 0 0 0 0 0 0 w - - - - - - - bromen 31h r 0 0 0 0 0 0 0 0 w bmar15 bmar14 bmar13 bmar12 bmar11 - - - 32h r/w 0 0 0 0 0 0 0 0 33h r/w 0 0 0 0 0 0 0 0 34h cap-ptr r ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0 35h | 3bh - reserved(all 0) 3ch ilr r/w 0 0 0 0 0 0 0 0 3dh ipr r 0 0 0 0 0 0 0 1 3eh mngnt r 0 0 1 0 0 0 0 0 3fh mxlat r 0 0 1 0 0 0 0 0 40h | ffh - reserved(all 0) www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 44 track id: jatr-1076-21 rev. 1. 6 8.4. pci power management functions the RTL8139C(l) is compliant to acpi (rev 1.0, 1.0b, 2.0) , pci power management (rev 1.1), and network device class power management reference specification (v1.0, 1.0a, 2.0), such as to support os directed power management (ospm) environment. to support this, the rtl 8139c(l) provides the following capabilities: ? the RTL8139C(l) can monitor the network for a wakeup frame, a magic packet, or a link change, and notify the system via pme# when such a packet or event arrives. then, the whole system can be restored to a working state to process the incoming jobs. ? the RTL8139C(l) can be isolated from the pci bus automatically with the auxiliary power ci rcuit when the pci bus is in b3 state, i.e. when the power on the pci bus is re moved. when the motherboard includes a built-in RTL8139C(l) single-chip fast ethernet controller, th e RTL8139C(l) can be disabled when needed by pulling the isolate pin low to 0v. when the RTL8139C(l) is in power down mode (d1 ~ d3): ? the rx state machine is stopped, and the RTL8139C(l) keeps monitoring the network for wakeup events such as magic packet, wakeup frame, and/or link change, in order to wake up the system. when in power down mode, the RTL8139C(l) will not reflect the st atus of any incoming packets in the isr regi ster and will not recei ve any packets into the rx fifo. ? the fifo status and the packets which ar e already contained in the rx fifo before entering power down mode are kept by the RTL8139C(l) during power down mode. ? the transmission is stopped. the action of pci bus master mode is stopped, as well. the tx fifo is kept. ? after restoration to a d0 state, the pci bus master mode continues to transfer the data, which is not yet moved into the tx fifo from the last break. the packet that was not transmitted completely last time is transmitted again. d3cold_support_pme bit(bit15, pmc re gister) & aux_i_b2:0 (bit8:6, pmc regi ster) in pci configuration space. if 9346 d3cold_support_pme bit(bit15, pmc) = 1, the above 4 bits depend on the existence of aux. power. if 9346 d3cold_support_pme bit(bit15, pmc) = 0, the above 4 bits are all 0's. examples: 1. if 9346 d3c_support_pme = 1, ? if aux. power exists, then pmc in pci config space is the same as 9346 pmc, i.e. if 9346 pmc = c2 f7, then pci pmc = c2 f7. ? if aux. power is absent, then pmc in pci config space is the same as 9346 pmc except the above 4 bits are all 0?s. i.e. if 9346 pmc = c2 f7, the pci pmc = 02 76. ? in this case, if wakeup support is desired when the main power is off, it is suggested that the 9346 pmc be set to: c2 f7 (rt 9346 default value). it is not recommended to set the d0_support_pme bit to ?1?. 2. if 9346 d3c_support_pme = 0, ? if aux. power exists, then pmc in pci config space is the same as 9346 pmc. i.e. if 9346 pmc = c2 77, then pci pmc = c2 77. ? if aux. power is absent, then pmc in pci config space is the same as 9346 pmc except the above 4 bits are all 0?s. i.e. if 9346 pmc = c2 77, the pci pmc = 02 76. ? in this case, if wakeup support is not desired when the main power is off, it is suggested that the 9346 pmc to be 02 76. it is not recommended to set the d0_support_pme bit to ?1?. a link wakeup occurs only when the following conditions are met: ? the linkup bit (config3#4) is set to 1, the pmen bit (config1#0) is set to 1, and the RTL8139C(l) is in an isolation state, or the pme# can be asserted in current power state. ? the link status is re-established. a magic packet wakeup occurs only when the following conditions are met: ? the destination address of the received magic packet matches. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 45 track id: jatr-1076-21 rev. 1. 6 ? the received magic packet doe s not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen bit (config1#0) is set to 1, and the RTL8139C(l) is in isolation state, or the pme# can be asse rted in current power state. ? the magic packet pattern matches, i.e. 6 * ffh + misc(can be none)+ 16 * did(destination id) in any part of a valid (fast) ethernet packet. a wakeup frame event occurs only wh en the following conditions are met: ? the destination address of the received wakeup frame matches. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. ? the 8-bit crc * (or 16-bit crc) of the received wake up frame matches with the 8-bit crc * (or 16-bit crc) of the sample wakeup frame pattern received from the local machine?s os. ? the last masked byte ** of the received wakeup frame matches with the last masked byte of the sample wakeup frame pattern provided by the local machine?s os. (in long wakeup fr ame mode, the last masked byte field is replaced with the high byte of the 16-bit crc.) * 8-bit crc: this 8-bit crc logic is used to generate an 8-bit crc from the masked by tes of the received wakeup frame packet within offset 12 to 75. software should calculate the 8-bit power management crc for each speci fic sample wakeup frame and store the calculated crc in the corresponding crc register for the RTL8139C(l) to check if ther e is a wakeup frame packet coming in. * 16-bit crc: (long wakeup frame mode, the mask bytes cover from offset 0 to 127): long wakeup frame: the RTL8139C(l) also supports 3 long wakeup frames. if the range of the mask bytes of the sample wakeup frame, passed down by the os to th e driver, exceeds the range from offset 12 to 75, the related registers of wakeup frames 2 and 3 can be merged to support one long wakeup fra me by setting the longwf (bit0, config4). thus, the range of effective mask bytes extends from offs et 0 to 127. the low byte and high byte of the calculated 16-bit crc should be put into register crc2 and lsbcrc2 respectiv ely. the mask bytes (16 bytes) shoul d be stored to register wakeup2 and wakeup3. the crc3 and lsbcrc3 have no meaning in this case and should be reset to 0. the long wakeup frame pairs are wakeup frames 4 and 5, wakeup frames 6 and 7. the crc5, crc7, lsbcrc5, and lsbcrc7 have no meaning in this case and should be reset to 0, if the RTL8139C(l) is set to support long wakeup frames. in this case, the RTL8139C(l) supports 5 wakeup frames, that are 2 norma l wakeup frames and 3 long wakeup frames. ** last masked byte: the last byte of the masked bytes of the received wakeup frame packet within offset 12 to 75 (in 8-bit crc mode) should match the last byte of the masked bytes of the sample wakeup frame provided by the local machine?s os. the pme# signal is asserted only when the following conditions are met: ? the pmen bit (bit0, config1) is set to 1. ? the pme_en bit (bit8, pm csr) in pci configuration space is set to 1. ? the RTL8139C(l) may assert pme# in current power state, or the RTL8139C(l) is in isolation state. refer to pme_support(bit15-11) of the pmc regi ster in pci configuration space. ? magic packet, linkup, or wakeup frame has occurred. note: writing a 1 to the pme_status (bit 15) of the pmcsr register in the pci configuration space will clear this bit and cause the RTL8139C(l) to stop asserting a pme# (if enabled). when the RTL8139C(l) is in power down mode, ex. d1-d3, the io, mem, and boot rom space are all disabled. after rst# is asserted, the power state must be change d to d0 if the original power state is d3 cold . there is no hardware enforced delays at RTL8139C(l)?s power state. when in acpi mode, the RTL8139C (l) does not support pme from d0, due to the setting of the pmc register. this setting comes from eeprom. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 46 track id: jatr-1076-21 rev. 1. 6 the RTL8139C(l) also supports the lan wake-up function. the lwake pin is used to notify the motherboard to execute the wake-up process whenever the RTL8139C(l) r eceives a wakeup event, such as magic packet. the lwake signal is asserted according the following setting. ? lwpme bit (bit4, config4): 0: the lwake is asserted whenev er there is wakeup event occurs. 1: the lwake can only be asserted when the pm eb is asserted and the isolateb is low. ? bit1 of delay byte(offset 1fh, eeprom): 0: lwake signal is disabled. 1: lwake signal is enabled 8.5. vital product data (vpd) bit 31 of the vpd is used to issue the vpd read/write command and is also a flag used to indicate if the transfer of data betwe en the vpd data register and the 93c46/93c56 has been completed or not. 1. write vpd register: (write data to 93c46/93c56)write the flag bit to a one at the same time the vpd address is written. when the flag bit is set to zero by the RTL8139C(l), the vpd data (all 4 bytes) has been transferred from the vpd data register to 93c46/93c56. 2. read vpd register: (read data from 93c46/93c56) write the flag bit to a zero at the same time the vpd address is written. when the flag bit is set to one by the RTL8139C(l), the vp d data (all 4 bytes) has been transferred from the 93c46/93c56 to the vpd data register. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 47 track id: jatr-1076-21 rev. 1. 6 9. functional description 9.1. transmit operation the host cpu initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. when the entire packet has been transferred to the tx buffer, the RTL8139C (l) is instructed to move the data from the tx buffer to the internal transmit fifo in pci bus master mode. when the tran smit fifo contains a complete packet or is filled to the programmed threshold level, the RTL8139C(l) begins packet transmission. 9.2. receive operation the incoming packet is placed in the RTL8139C(l)'s rx fifo. concurrently, the RTL8139C(l) performs address filtering of multicast packets according to its hash algor ithms. when the amount of data in the rx fifo reaches the level defined in the receive configuration regi ster, the RTL8139C(l) requests the pc i bus to begin transferring the da ta to the rx buffer in pci bus master mode. 9.3. line quality monitor the line quality monitor function is availabl e in 100base-tx mode. it is possible to determine the amount of equalization being used by accessing certain test registers with the dsp engine. this provides a crude indicati on of connected cable length. this funct ion allows for a quick and simple verification of the line quality in that any significant deviation from an expected register valu e (based on a known cable length) would indicate that the signal quality has deviated from the expected nominal case. 9.4. clock recovery module the clock recovery module (crm) is s upported in both 10base-t and 100base-tx m ode. the crm accepts 125mb/s mlt3 data from the equalizer. the dpll locks onto the 125mb/s data stream and extracts a 125mhz recovered clock. the extracted and synchronized clock and data are used as re quired by the synchronous receive operations. 9.5. loopback operation loopback mode is normally used to verify that the logic operati ons up to the ethernet cable function correctly. in loopback mod e for 100mbps, the RTL8139C(l) takes frames from the transmit descriptor and transmits them up to internal twister logic. 9.6. tx encapsulation while operating in 100base-tx mode, the RTL8139C(l) encapsula tes the frames that it transm its according to the 4b/5b code-groups table. the changes of the original packet data are listed as follows: 1. the first byte of the preamble in the mac frame is replaced with the jk symbol pair. 2. after the crc, the tr symbol pair is inserted. 9.7. collision if the RTL8139C(l) is not in full-duplex mode, a collision even t occurs when the receive i nput is not idle while the RTL8139C(l) transmits. if the collision was de tected during the preamble transmission, the jam pattern is transmitted after completing the preamble (including the jk symbol pair). www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 48 track id: jatr-1076-21 rev. 1. 6 9.8. rx decapsulation the RTL8139C(l) continuously monitors the ne twork when reception is enabled. when ac tivity is recognized it starts to process the incoming data. after detecting receive activity on the lin e, the RTL8139C(l) starts to process th e preamble bytes based on the mode of operation. while operating in 100base-tx mode, the RTL8139C(l) expects the frame to start with the symbol pair jk in the first bye of the 8-byte preamble. the RTL8139C(l) checks the crc bytes and check s if the packet data ends with the tr symbol pair, if not, the RTL8139C(l) reports a crc error rsr. the RTL8139C(l) reports a rsr error in the following case: in 100base-tx mode, one of the following occur. a. an invalid symbol (4b/ 5b table) is received in the middle of the frame. the rsr bit also sets. b. the frame does not end with the tr symbol pair. 9.9. flow control the RTL8139C(l) supports ieee802.3x flow control to improve performance in full- duplex mode. it detects pause packets to achieve flow control tasks. 9.9.1. control frame transmission when the RTL8139C(l) detects that its free recei ve buffer is less than 3k bytes, it sends a pause packet with pause_time(=ffffh) to inform the source station to stop transmission for the specified period of time. after the driver has processed the packets in the receive buffer and update d the boundary pointer, the r tl8139c(l) sends the other pause packet with pause_time(=0000h) to wake up the source station to restart transmission. 9.9.2. control frame reception the RTL8139C(l) enters a back off state for a sp ecified period of time when it receives a valid pause packet with pause_time(=n) . if the pause packet is received while the RTL8139C(l) is transmitting, the RTL8139C(l) starts to back off after current transmission completes. the RTL8139C(l) is free to transmit the next packets when it receives a valid pause packet with pause_time(=0000h) or the backoff timer(=n*512 bit time) elapses. note: the pause operation cannot be used to inhibit transmission of mac control frames (e.g. a pause packet). the n-way flow control capability can be disabled. please refer to section 7, ?eeprom (93c46 or 93c56) contents? for a detailed description. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 49 track id: jatr-1076-21 rev. 1. 6 9.10. led functions 9.10.1. 10/100mbps link monitor the link monitor senses the link integrity or if a station is down. 9.10.2. led_rx in 10/100 mbps mode, the led function is as follows: receiving packet? power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no 9.10.3. led_tx power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no transmitting packet www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 50 track id: jatr-1076-21 rev. 1. 6 9.10.4. led_tx+led_rx power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no tx or rx packet? www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 51 track id: jatr-1076-21 rev. 1. 6 10. application diagram RTL8139C(l) rj45 magetics eeprom boot rom led clk data address pci interface auxiliary power www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 52 track id: jatr-1076-21 rev. 1. 6 11. electrical characteristics 11.1. temperature limit ratings parameter minimum maximum units storage temperature -55 +125 c operating temperature 0 70 c 11.2. dc characteristics 11.2.1. supply voltage vcc = 3.0v min. to 3.6v max. symbol parameter conditions minimum maximum units v oh minimum high level output voltage i oh= -8ma 0.9 * vcc vcc v v ol maximum low level output voltage i ol= 8ma 0.1 * vcc v v ih minimum high level input voltage 0.5 * vcc vcc+0.5 v v il maximum low level input voltage -0.5 0.3 * vcc v i in input current v in= v cc or gnd -1.0 1.0 ua i oz tri-state output leakage current v out= v cc or gnd -10 10 ua i cc average operating supply current i out= 0ma, 150 ma www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 53 track id: jatr-1076-21 rev. 1. 6 11.3. ac characteristics 11.3.1. flash/boot rom timing flash/boot rom - read md7-0 ma17-0 romcsb oeb web tcolz toh tohz tacc toolz trc tce toes twrbr symbol description minimum typical maximum units trc read cycle 135 - - ns tce chip enable access time - - 200 ns tacc address access time - - 200 ns toes output enable access time - - 60 ns tcolz chip enable to output in low z 0 - - ns toolz output enable to output in low z 0 - - ns tohz output disable to output in high z - - 40 ns toh output hold from address, romcsb, or oeb 0 - 0 ns twrbr write recovery time before read 6 - - us www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 54 track id: jatr-1076-21 rev. 1. 6 flash memory - write md7-0 ma17-0 romcsb oeb web programming program verification program command latch address & data verify command standby/vcc power-down setupmprogram command vcc power-up & standby twc twc trc tch tas tdh tghwl datao tds twp twhgl dataout =c0h dataout =40h valid data in twph twhwh1 twp tds tdh tcs tah tds tcolz twp tch tah tcs tdf tce toolz toe toh symbol description minimum typical maximum units twc write cycle time 135 - - ns tas address set-up time 0 - - ns tah address hold time 60 - - ns tds data set-up time 50 - - ns tdh data hold time 10 - - ns twhgl write recovery time before read 6 - - us tghwl read recovery time before write 0 - - us tcs chip enable set-up time before write 20 - - ns tch chip enable hold time 0 - - us twp write pulse width 50 - - ns twph write pulse width high 20 - - ns twhwh1 duration of programming operation 10 - 25 us www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 55 track id: jatr-1076-21 rev. 1. 6 11.3.2. pci bus operation timing target read target write www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 56 track id: jatr-1076-21 rev. 1. 6 configuration read configuration write www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 57 track id: jatr-1076-21 rev. 1. 6 bus arbitration memory read www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 58 track id: jatr-1076-21 rev. 1. 6 memory write target initiated termination - retry www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 59 track id: jatr-1076-21 rev. 1. 6 target initiated termination - disconnect target initiated termination - abort www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 60 track id: jatr-1076-21 rev. 1. 6 master initiated termination - abort parity operation - one example www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 61 track id: jatr-1076-21 rev. 1. 6 12. mechanical dimensions (128-pin qfp) note: symbol dimension in inch dimension in mm 1. dimension d & e do not include interlead flash. min typical max min typical max 2. dimension b does not include dambar protrusion/intrusion. a - 0.134 - - 3.40 3. contro lling dimension: millimeter a1 0.004 0.010 0.036 0.10 0.25 0.91 4. general appearance spec. should be based on final visual a2 0.102 0.112 0.122 2.60 2.85 3.10 inspection spec. b 0.005 0.009 0.013 0.12 0.22 0.32 c 0.002 0.006 0.010 0.05 0.15 0.25 d 0.541 0.551 0.561 13.75 14.00 14.25 title: 128 qfp (14x20 mm ) package outline e 0.778 0.787 0.797 19.75 20.00 20.25 -cu l/f, footprint 3.2 mm 0.020 bsc 0.50 bsc leadframe material: h d 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. 530-ass-p004 h e 0.902 0.913 0.925 22.90 23.20 23.50 version 1 l 0.027 0.035 0.043 0.68 0.88 1.08 page of l 1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y - - 0.004 - - 0.10 date nov. 4 1999 0 - 12 0 - 12 realtek semiconductor co., ltd www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 62 track id: jatr-1076-21 rev. 1. 6 13. mechanical dimensions (128-pin lqfp) note: symbol dimension in inch dimension in mm 1.dimension b does not include dambar protrusion/intrusion. min typical max min typical max 2.controlling dimension: millimeter a - - 0.067 - - 1.70 3.general appearance sp ec. should be based on final visual a1 0.000 0.004 0.008 0.00 - 0.25 a2 0.051 0.055 0.059 1.30 1.40 1.50 b 0.006 0.009 0.011 0.15 0.22 0.29 c 0.004 - 0.006 0.09 - 0.20 title: 128ld lqfp ( 14x20x1.4 m m*2 ) package d 0.541 0.551 0.561 13.75 14.00 14.25 -cu l/f, footprint 2.0 mm e 0.778 0.787 0.797 19.75 20.00 20.25 leadframe material: 0.020 bsc 0.50 bsc approve doc. no. 530-ass-p004 h d 0.620 0.630 0.640 15.90 16.00 16.30 version 1 h e 0.855 0.866 0.877 21.70 22.00 23.30 page of l 0.016 0.024 0.031 0.45 0.60 0.75 check dwg no. lq128 - 1 l 1 0.039 ref 1.00 ref date nov. 4.1999 0 3.5 9 0 3.5 9 realtek semiconductor corp. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8139C(l) datasheet 3.3v single-chip fast ethernet controller w/power management 63 track id: jatr-1076-21 rev. 1. 6 14. ordering information table 1. ordering information part number package status RTL8139C 128-pin qfp RTL8139C-lf 128-pin qfp lead (pb)-free RTL8139Cl 128-pin lqfp RTL8139Cl-lf 128-pin lqfp lead (pb)-free note: see page 4 for lead (pb)-free package and version identification. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/

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